TN2529
Low Threshold N-Channel
Enhancement-Mode Vertical DMOS FET
Features
►
Low threshold - 2.0V max
►
High input impedance
►
Low input capacitance - 125pF max
►
Fast switching speeds
►
Low ON-resistance
►
Free from secondary breakdown
►
Low input and output leakage
General Description
The Supertex TN2529 is a low threshold enhancement-
mode transistor that utilizes an advanced vertical
DMOS structure and Supertex’s well-proven silicon-gate
manufacturing process. This combination produces a device
with the power handling capabilities of bipolar transistors,
and the high input impedance and positive temperature
coefficient inherent in MOS devices. Characteristic of all
MOS structures, this device is free from thermal runaway
and thermally-induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
Applications
►
Logic level interfaces – ideal for TTL and CMOS
►
Solid state relays
►
►
►
►
►
Battery operated systems
Photo voltaic devices
Analog switches
General purpose line drivers
Telecom switches
Switching Waveforms and Test Circuit
V
DD
10V
90%
INPUT
0V
10%
t
(ON)
PULSE
GENERATOR
t
(OFF)
t
r
t
d(OFF)
t
F
R
L
OUTPUT
R
GEN
t
d(ON)
V
DD
10%
10%
INPUT
D.U.T.
OUTPUT
0V
90%
90%
TN2529
Ordering Information
Package Options
Device
14-Lead QFN
5x5mm body, 1.0mm height (max), 1.27mm pitch
BV
DSS
/BV
DGS
(V)
290
R
DS(ON)
(max)
(Ω)
V
GS(th)
(max)
I
D(ON)
(min)
(V)
2.0
(A)
1.0
TN2529
TN2529K6-G
6.0
-G indicates package is RoHS compliant (‘Green’)
Product Marking
TN2529
LLLLLL
YYWW
AAACCC
L = Lot Number
YY = Year Sealed
WW = Week Sealed
A = Assembler ID
C = Country of Origin
= “Green” Packaging
Absolute Maximum Ratings
Parameter
Drain to source voltage
Drain to gate voltage
Gate to source voltage
Operating and storage temperature
Maximum junction temperature
Value
BV
DSS
BV
DGS
±20V
-55°C to +150°C
150°C
NC 11
14-Lead QFN
Pin Configuration
DRAIN
14
DRAIN
13
DRAIN
12
11 GATE
Absolute Maximum Ratings are those values beyond which damage to
the device may occur. Functional operation under these conditions is not
implied. Continuous operation of the device at the absolute rating level
may affect device reliability. All voltages are referenced to device ground.
SOURCE 2
10 SOURCE
SOURCE 3
9 SOURCE
SOURCE 4
5
DRAIN
6
DRAIN
(top view)
8 SOURCE
7
DRAIN
14-Lead QFN
Thermal Characteristics
I
D
Package
14-Lead QFN
(continuous)
(mA)
I
D
(pulsed)
(A)
Power Dissipation
@T
A
= 25
O
C
(W)
O
θ
jc
( C/W)
O
θ
ja
( C/W)
I
DR
(
mA)
410
†
I
DRM
(
A)
2.0
410
†
2.0
2.0
‡
30
62.5
Notes:
† I
D
(continuous) is limited by max rated T
J
of 150
O
C
.
.
‡ Mounted on FR4 board, 25mm x 25mm x 1.57mm.
2
TN2529
Electrical Characteristics
(T = 25°C unless otherwise specified)
A
Symbol
Parameter
Min
Typ
Max
Units
Conditions
BV
DSS
V
GS(th)
ΔV
GS(th)
I
GSS
Drain-to-source breakdown voltage
Gate threshold voltage
V
GS(th)
change with temperature
Gate body leakage current
290
0.6
-
-
-
-
-
-
-
-
-
1.9
2.8
4.0
4.0
-
600
65
35
10
-
-
-
-
-
300
-
2.0
-5.0
100
10
1.0
-
V
V
mV/
O
C
nA
µA
mA
V
GS
= 0V, I
D
= 2.0mA
V
GS
= V
DS
, I
D
= 1.0mA
V
GS
= V
DS
, I
D
= 1.0mA
V
GS
= ±20V, V
DS
= 0V
V
GS
= 0V, V
DS
= Max rating
V
DS
= 0.8 Max Rating,
V
GS
= 0V, T
A
= 125
O
C
V
GS
= 4.5V, V
DS
= 25V
V
GS
= 10V, V
DS
= 25V
I
DSS
Zero gate voltage drain current
-
0.5
I
D(ON)
ON-state drain current
1.0
Static drain-to-source ON-state
resistance
Change in R
DS(ON)
with temperature
Forward transconductance
Input capacitance
Common source output capacitance
Reverse transfer capacitance
Turn-ON delay time
Rise time
Turn-OFF delay time
Fall time
Diode forward voltage drop
Reverse recovery time
-
-
-
300
-
-
-
-
-
-
-
-
-
-
6.0
A
R
DS(ON)
ΔR
DS(ON)
G
FS
C
ISS
C
OSS
C
RSS
t
d(ON)
t
r
t
d(OFF)
t
f
V
SD
t
rr
Ω
6.0
1.4
-
125
70
25
10
10
ns
20
20
1.8
-
V
ns
pF
%/
O
C
mmho
V
GS
= 4.5V, I
D
= 250mA
V
GS
= 10V, I
D
= 500mA
V
GS
= 10V, I
D
= 500mA
V
DS
= 25V, I
D
= 500mA
V
GS
= 0V,
V
DS
= 25V,
f = 1.0MHz
V
DD
= 25V,
I
D
= 1.0A,
R
GEN
= 25Ω
V
GS
= 0V, I
SD
= 1.0A
V
GS
= 0V, I
SD
= 1.0A
Notes:
1.All D.C. parameters 100% tested at 25
O
C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2.All A.C. parameters sample tested.
3
TN2529
14-Lead QFN Package Outline (K6)
5x5mm body, 1.0mm height (max), 1.27mm pitch
14
D
E2
14
Pin 1
1
Note 1
(Index Area
D/2 x E/2)
E
D2
Note 1
(Index Area
D/2 x E/2)
e
Exposed
Pad
b
e
DD
CC
AA
BB
Top View
θ
Bottom View
A
A3
Seating
Plane
A1
Side View
Notes:
1. Details of Pin 1 identifier are optional, but must be located within the indicated area. The Pin 1 identifier may be either a mold, or a marked feature.
Symbol
MIN
Dimension
(mm)
NOM
MAX
Drawings not to scale.
A
0.80
0.90
1.00
A1
0.00
0.02
0.05
A3
0.20
REF
b
0.46
0.51
0.58
D
4.85
5.00
5.15
D2
4.45
4.50
4.55
E
4.85
5.00
5.15
E2
2.52
2.57
2.62
e
1.27
BSC
AA
0.152
0.252
0.352
BB
0.473
0.523
0.583
CC
0.66
0.71
0.77
DD
0.456
0.506
0.566
θ
0
O
-
14
O
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to
http://www.supertex.com/packaging.html.)
Doc.# DSFP-TN2529
NR061107
4
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