®
82C55A
Data Sheet
November 16, 2006
FN2969.10
CMOS Programmable Peripheral Interface
The Intersil 82C55A is a high performance CMOS version of
the industry standard 8255A and is manufactured using a
self-aligned silicon gate CMOS process (Scaled SAJI IV). It
is a general purpose programmable I/O device which may
be used with many different microprocessors. There are 24
I/O pins which may be individually programmed in 2 groups
of 12 and used in 3 major modes of operation. The high
performance and industry standard configuration of the
82C55A make it compatible with the 80C86, 80C88 and
other microprocessors.
Static CMOS circuit design insures low operating power. TTL
compatibility over the full military temperature range and bus
hold circuitry eliminate the need for pull-up resistors. The
Intersil advanced SAJI process results in performance equal
to or greater than existing functionally equivalent products at
a fraction of the power.
Features
• Pb-Free Plus Anneal Available (RoHS Compliant)
(See Ordering Info)
• Pin Compatible with NMOS 8255A
• 24 Programmable I/O Pins
• Fully TTL Compatible
• High Speed, No “Wait State” Operation with 5MHz and
8MHz 80C86 and 80C88
• Direct Bit Set/Reset Capability
• Enhanced Control Word Read Capability
• L7 Process
• 2.5mA Drive Capability on All I/O Ports
• Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . . . .10μA
Ordering Information
PART NUMBERS
5MHz
CP82C55A-5
CP82C55A-5Z (Note)
PART
MARKING
CP82C55A-5
8MHz
CP82C55A
PART
MARKING
CP82C55A
CP82C55AZ
IP82C55A
IP82C55AZ
CS82C55A*
TEMP.
RANGE (°C)
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
-40 to +85
-55 to +125
SMD#
SMD#
44 Ld CLCC
J44.A
PACKAGE
40 Ld PDIP
40 Ld PDIP (Pb-free)
40 Ld PDIP
40 Ld PDIP (Pb-free)
44 Ld PLCC
44 Ld PLCC (Pb-free)
44 Ld PLCC
44 Ld PLCC (Pb-free)
44 Ld MQFP
44 Ld MQFP (Pb-free)
44 Ld MQFP
44 Ld MQFP (Pb-free)
40 Ld CERDIP
F40.6
Q44.10x10
N44.65
PKG. DWG. #
E40.6
CP82C55A-5Z CP82C55AZ (Note)
IP82C55A
IP82C55AZ (Note)
CS82C55A-5*
CS82C55A-5Z* (Note)
IS82C55A-5*
IS82C55A-5Z* (Note)
CS82C55A-5
CS82C55A*
CS82C55A-5Z CS82C55AZ* (Note) CS82C55AZ
IS82C55A-5
IS82C55A-5Z
IS82C55A*
IS82C55AZ* (Note)
CQ82C55A*
CQ82C55AZ (Note)
IQ82C55A*
IQ82C55AZ* (Note)
ID82C55A
MD82C55A/B
8406602QA
8406602XA
IS82C55A*
IS82C55AZ
CQ82C55A*
CQ82C55AZ
IQ82C55A*
IQ82C55AZ
ID82C55A
MD82C55A/B
8406602QA
8406602XA
*Add “96” suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-
free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002, 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
82C55A
Functional Description
Data Bus Buffer
This three-state bidirectional 8-bit buffer is used to interface
the 82C55A to the system data bus. Data is transmitted or
received by the buffer upon execution of input or output
instructions by the CPU. Control words and status
information are also transferred through the data bus buffer.
POWER
SUPPLIES
+5V
GND
GROUP A
CONTROL
GROUP A
PORT A
(8)
I/O
PA7-
PA0
Read/Write and Control Logic
The function of this block is to manage all of the internal and
external transfers of both Data and Control or Status words.
It accepts inputs from the CPU Address and Control busses
and in turn, issues commands to both of the Control Groups.
(CS)
Chip Select. A “low” on this input pin enables the
communication between the 82C55A and the CPU.
(RD)
Read. A “low” on this input pin enables 82C55A to send
the data or status information to the CPU on the data bus. In
essence, it allows the CPU to “read from” the 82C55A.
(WR)
Write. A “low” on this input pin enables the CPU to
write data or control words into the 82C55A.
(A0 and A1)
Port Select 0 and Port Select 1. These input
signals, in conjunction with the RD and WR inputs, control
the selection of one of the three ports or the control word
register. They are normally connected to the least significant
bits of the address bus (A0 and A1).
82C55A BASIC OPERATION
A1
0
0
1
1
A0
0
1
0
1
RD
0
0
0
0
WR
1
1
1
1
CS
0
0
0
0
INPUT OPERATION
(READ)
Port A
→
Data Bus
Port B
→
Data Bus
Port C
→
Data Bus
Control Word
→
Data Bus
OUTPUT OPERATION
(WRITE)
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
Data Bus
→
Port A
Data Bus
→
Port B
Data Bus
→
Port C
Data Bus
→
Control
DISABLE FUNCTION
X
X
X
X
X
1
X
1
1
0
Data Bus
→
Three-State
Data Bus
→
Three-State
BIDIRECTIONAL
DATA BUS
DATA
BUS
D7-D0
BUFFER
GROUP A
PORT C
UPPER
(4)
8-BIT
INTERNAL
DATA BUS
GROUP B
PORT C
LOWER
(4)
I/O
PC7-
PC4
I/O
PC3-
PC0
RD
WR
A1
A0
RESET
READ
WRITE
CONTROL
LOGIC
GROUP B
CONTROL
GROUP B
PORT B
(8)
I/O
PB7-
PB0
CS
FIGURE 1. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER,
READ/WRITE, GROUP A & B CONTROL LOGIC
FUNCTIONS
Group A and Group B Controls
The functional configuration of each port is programmed by
the systems software. In essence, the CPU “outputs” a
control word to the 82C55A. The control word contains
information such as “mode”, “bit set”, “bit reset”, etc., that
initializes the functional configuration of the 82C55A.
Each of the Control blocks (Group A and Group B) accepts
“commands” from the Read/Write Control logic, receives
“control words” from the internal data bus and issues the
proper commands to its associated ports.
Control Group A - Port A and Port C upper (C7 - C4)
Control Group B - Port B and Port C lower (C3 - C0)
The control word register can be both written and read as
shown in the “Basic Operation” table. Figure 4 shows the
control word format for both Read and Write operations.
When the control word is read, bit D7 will always be a logic
“1”, as this implies control word mode information.
Ports A, B, and C
The 82C55A contains three 8-bit ports (A, B, and C). All can
be configured to a wide variety of functional characteristics
by the system software but each has its own special features
or “personality” to further enhance the power and flexibility of
the 82C55A.
Port A
One 8-bit data output latch/buffer and one 8-bit data
input latch. Both “pull-up” and “pull-down” bus-hold devices
are present on Port A. See Figure 2A.
Port B
One 8-bit data input/output latch/buffer and one 8-bit
data input buffer. See Figure 2B.
Port C
One 8-bit data output latch/buffer and one 8-bit data
input buffer (no latch for input). This port can be divided into
(RESET)
Reset. A “high” on this input initializes the control
register to 9Bh and all ports (A, B, C) are set to the input
mode. “Bus hold” devices internal to the 82C55A will hold
the I/O port inputs to a logic “1” state with a maximum hold
current of 400μA.
4
FN2969.10
November 16, 2006
82C55A
two 4-bit ports under the mode control. Each 4-bit port
contains a 4-bit latch and it can be used for the control signal
output and status signal inputs in conjunction with ports A
and B. See Figure 2B.
INPUT MODE
MASTER
RESET
OR MODE
CHANGE
INTERNAL
DATA IN
INTERNAL
DATA OUT
(LATCHED)
OUTPUT MODE
EXTERNAL
PORT A PIN
MODE 0
RD, WR
D7-D0
82C55A
C
B
8
I/O
4
I/O
4
I/O
A
8
I/O
A0-A1
CS
ADDRESS BUS
CONTROL BUS
DATA BUS
PB7-PB0
MODE 1
PC3-PC0
C
PC7-PC4
PA7-PA0
FIGURE 2A. PORT A BUS-HOLD CONFIGURATION
B
8
P
PB7-PB0
MODE 2
INTERNAL
DATA IN
INTERNAL
DATA OUT
(LATCHED)
OUTPUT MODE
EXTERNAL
PORT B, C
PIN
CONTROL CONTROL
OR I/O
OR I/O
C
I/O
PA7-PA0
I/O
A
8
I/O
RESET
OR MODE
CHANGE
V
CC
B
8
A
BI-
DIRECTIONAL
PB7-PB0
CONTROL
PA7-PA0
FIGURE 2B. PORT B AND C BUS-HOLD CONFIGURATION
FIGURE 2. BUS-HOLD CONFIGURATION
FIGURE 3. BASIC MODE DEFINITIONS AND BUS INTERFACE
Operational Description
Mode Selection
There are three basic modes of operation than can be
selected by the system software:
Mode 0 - Basic Input/Output
Mode 1 - Strobed Input/Output
Mode 2 - Bidirectional Bus
When the reset input goes “high”, all ports will be set to the
input mode with all 24 port lines held at a logic “one” level by
internal bus hold devices. After the reset is removed, the
82C55A can remain in the input mode with no additional
initialization required. This eliminates the need to pull-up or
pull-down resistors in all-CMOS designs. The control word
register will contain 9Bh. During the execution of the system
program, any of the other modes may be selected using a
single output instruction. This allows a single 82C55A to
service a variety of peripheral devices with a simple software
maintenance routine. Any port programmed as an output
port is initialized to all zeros when the control word is written.
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
GROUP B
PORT C (LOWER)
1 = INPUT
0 = OUTPUT
PORT B
1 = INPUT
0 = OUTPUT
MODE SELECTION
0 = MODE 0
1 = MODE 1
GROUP A
PORT C (UPPER)
1 = INPUT
0 = OUTPUT
PORT A
1 = INPUT
0 = OUTPUT
MODE SELECTION
00 = MODE 0
01 = MODE 1
1X = MODE 2
MODE SET FLAG
1 = ACTIVE
FIGURE 4. MODE DEFINITION FORMAT
5
FN2969.10
November 16, 2006
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