MT91610
Analog Ringing SLIC
Preliminary Information
Features
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Transformerless 2W to 4W conversion
Controls battery feed to line
Programmable line impedance
Programmable network balance impedance
Off-hook and dial pulse detection
Protects against GND short circuit
Programmable gain
Programmable constant current mode with
constant voltage fold over
Transformerless balanced ringing with
automatic ring trip circuit. No mechanical relay
Supports low voltage ringing
Line polarity reversal
On-hook transmission
Power down and wake up capability
Meter pulse injection
Ground Key detection
DS5181
ISSUE 2
February 2000
Package Information
MT91610AQ
36 Pin QSOP Package
-40°C to +85°C
Description
The Mitel MT91610, with an external bipolar driver
(Figure 4), provides an interface between a switching
system and a subscriber loop. The functions
provided by the MT91610 include battery feed,
programmable constant current with constant voltage
fold over for long loop, 2W to 4W conversion, off-
hook and dial pulse detection, direct balance ringing
with built in ring tripping, unbalance detection, user
definable line and network balance impedance’s and
gain, and power down and wake up. The device is
fabricated as a CMOS circuit in a 36 pin QSOP
package.
Applications
Line interface for:
• PABX
• Intercoms
• Key Telephone Systems
• Control Systems
RV
PD
GTX1 ESE
ESI
GTX0
VX
TD
RD
Tip/Ring Drive
Controller
Audio Gain & Network
Balance Circuit
VR
TIP
RING
RF1, RF2
Line Sense
2 W to 4 W
Conversion & Line
Impedance
Over-Current
Protection Circuit
Z3
Z2
CP5
Line
Reverse
Driver
LR
RC
CP4
CP6
CP7
Ring Drive
Controller
Loop Supervision
CP2
CP3
VDD
VREF
GND
VEE
Figure 1 - Functional Block Diagram
VBAT
DCRI
SHK
UD
CP1
1
MT91610
VDD
TD
TF1
NC
TIP
VREF
LR
RING
RF1
NC
RD
CP1
CP2
CP3
CP4
ESE
PD
DCRI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
VEE
RV
CP7
SHK
VBAT
UD
RC
CP6
VR
GTX1
ESI
VX
GTX0
Z3
Z2
CP5
Z1
AGND
Preliminary Information
Figure 2 - Pin Connections
Pin Description
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Name
VDD
TD
TF1
NC
Tip
VREF
LR
Ring
RF1
NC
RD
CP1
CP2
CP3
CP4
ESE
PD
DCRI
AGND
Positive supply rail, +5V.
Tip Drive (Output).
Controls the Tip transistor. Connects 150nF cap to GND.
Tip Feed 1 (Output).
Connects to the Tip transistor and to TIP via the Tip feed resistor.
No Connection
Left open
Tip.
Connects to the TIP lead of the telephone line.
Reference Voltage (Input).
Used to set the subscribers loop constant current. A 0.1uF
cap should be connected between this pin and GND for noise decoupling.
Line Reverse (Input).
This pin should be set to 0V for NORMAL polarity. Setting the pin
to +5V reverses the polarity of Tip and Ring
Ring.
Connects to the RING lead of the telephone line
Ring Feed 1 (Output).
Connects to the RING lead via the Ring feed resistor
No Connection
Left open
Ring Drive (Output).
Controls the Ring transistor. Connects 150nF cap to GND.
CP1.
A 220nF capacitor should be connected between this pin and pin 13
CP2.
A 330nF capacitor for loop stability is connected between this pin and pin 14
CP3.
A 330nF capacitor for loop stability is connected between this pin and pin 13
CP4.
A 100nF cap should be connected between this pin and GND
External Signal Enable (Input).
A logic ’1’ enable the MPI (Meter Pulse Input) to Tip /
Ring. This pin should be set to logic ’0’ when not used.
Power Down (Input).
A logic ’1’ power down the device. This pin should be set to logic ’0’
for normal operation.
DC voltage for Ringing Input (Input)
The positive voltage supply for balance ringing.
The input DC voltage range is from 0V to +72V.
Analog Ground.
4 Wire Ground, normally connected to system ground.
Description
2
Preliminary Information
Pin Description (continued)
Pin #
20
21
22
23
24
25
26
27
28
29
30
Name
Z1
CP5
Z2
Z3
GTX0
VX
ESI
GTX1
VR
CP6
RC
Description
MT91610
Line Impedance Node 1.
A resistor of scaled value "k" is connected between Z1 and Z2.
This connection can not be left open circuit.
Line Impedance AC couple.
A 0.1uF cap must be connected between this pin and Z1
(pin 16)
Line Impedance Node 2.
This is the common connection node between Z1 and Z3.
Line Impedance Node 3.
A network either resistive or complex of scaled value "k" is
connected between Z3 and Z2. This connection can not be left open circuit.
Gain Node 0.
This is the common node between Z3 and VX where resistors are
connected to set the 2W to 4W gain.
Transmit Audio.
4W analog signal from the SLIC.
External Signal Input.
12 / 16 KHz signal input
Gain Node 1.
The common node between VR and the audio input from the CODEC or
switching network where resistors are fitted to sets the 4W to 2W gain
Receive Audio.
4W analog signal to the SLIC.
Ringing Cap.
A 0.47uF cap should be connected between this pin and GND for ringing
voltage filtering.
Ringing Control.
An active high (+5V) on this pin will set up the DC feed and gain of the
SLIC to apply 20 Hz ringing. When low (0V) set the SLIC in normal constant current mode
of operation.
UnBalance Detect.
To indicate an offset current between Tip and Ring
VBAT.
The negative battery supply, typically at -48V
Switch Hook.
This pin indicates the line state of the subscribers telephone. The output
can also be used for dial pulse monitoring. This pin is active high
Deglitching Cap.
A 33nF should be connected between this pin and GND
Ringing Voltage.
20 Hz sinusoidal or square wave AC in for balance ringing
Negative supply rail, -5V.
4 wire signal, which is the output from the SLIC to
the analog switch or voice CODEC.
components
31
32
33
34
35
36
UD
VBAT
SHK
CP7
RV
VEE
Functional Description
Refer to Figure
designation.
4
for
MT91610
Gain Control
It is possible to set the Transmit and Receive gains
by the selection of the appropriate external
components.
The gains can be calculated by the following
formulae:
2W to 4W gain
Gain 2 - 4 = 20 Log [ R8 / R7]
4W to 2W gain
Gain 4 - 2 = 20 Log [0.891 * [R10 / R9)]
The MT91610, with external bipolar transistors,
functions as an Analog Line SLIC for use in a 4 Wire
switched system. The SLIC performs all of the
BORSH functions whilst interfacing to a CODEC or
switching system.
2 Wire to 4 Wire conversion
The SLIC performs 2 wire to 4 wire conversion by
taking the 4 wire signal from an analog switch or
voice CODEC, and converting it to a 2 wire
differential signal at Tip and Ring. The 2 wire signal
applied to tip and ring by the phone is converted to a
3
MT91610
Impedance Programming
The MT91610 allows the designer to set the device’s
impedance across TIP and RING, (Z
TR
), and
network balance impedance, (Z
NB
), separately with
external low cost components.
The impedance (Z
TR
) is set by R4, R5, whilst the
network balance, (Z
NB
), is set by R6, R8, (see Figure
4.)
The network balance impedance should
calculated once the 2W - 4W gain has been set.
be
Preliminary Information
Loop Supervision
The Loop Supervision circuit monitors the state of
the phone line and when the phone goes "Off Hook"
the SHK pin goes high to indicate this state. This pin
reverts to a low state when the phone goes back "On
Hook" or if the loop resistance is too high (>2.3KΩ)
When loop disconnect dialing is being used, SHK
pulses to logic 0 indicate the digits being dialled.
This output should be debounced.
Constant Current Control & Voltage
Fold Over Mode
The SLIC employs a feedback circuit to supply a
constant feed current to the line. This design is
accomplished by sensing the sum of the voltages
across the feed resistors, Ra and Rb, and comparing
it to the input reference voltage, Vref, that
determines the constant current feed current.
By using a resistive divider network, (Figure 3), it is
possible to generate the required voltage to set the
I
LOOP
. This voltage can be calculated by the formula:
I
LOOP
= [ G * 5] * 3
(Ra +Rb)
where,
G = R2 / (R1 + R2)
I
LOOP
is in Ampere.
R1= 200KΩ
Ra = Rb = 100
Ω
R2 = 72.73 KΩ
R2 = 100 KΩ
R2 = 133.33 KΩ
Line Impedance
For optimum performance, the characteristic
impedance of the line, (Z
o
), and the device’s
impedance across TIP and RING, (Z
TR
), should
match. Therefore:
Z
o
= Z
TR
The relationship between Z
o
and the components
that set Z
TR
is given by the formula:
Z
o
/ ( Ra+Rb) = kZ
o
/ R4
where kZ
o
= R5
Ra = Rb
The value of k can be set by the designer to be any
value between 20 and 250. R4 and R5 should be
greater than 50kΩ.
Network Balance Impedance
The network balance impedance, (Z
NB
), will set the
transhybrid loss performance for the circuit. The
transhybrid loss of the circuit depends on both the 4 -
2 Wire gain and the 2 - 4 Wire gain.
The method of setting the values for R6 (or Z6... it
can be a complex impedance) is given as below:
R6 = R7 * (R9 / R10) * 2.2446689 * ( Z
NB
/ Z
NB
+ Z
o
)
From Figure 3 with
For I
LOOP
= 20mA,
For I
LOOP
= 25mA,
For I
LOOP
= 30mA,
R2
**kΩ
6
R1
200K
V
REF
C2
0.1uF
MT91610
+5V
Please note that in the case of Z
o
not equal to Z
NB
(the THL compromized case) R6 is a complex
impedance. In the general case of Z
o
matches to Z
NB
(the THL optimized case) R6 is just a single resistor.
** See Figure 6
Figure 3 - Loop Setting
For convenience, a graph which plots the value of
R2 (KΩ) versus the expected loop current is shown
in Figure 6.
4
Preliminary Information
As +5V is used as the reference voltage to generate
the loop current, any noise on the +5V rail will
deteriorate the PSR (Power Supply Rejection)
parameter of the SLIC. It is therefore important to
decouple +5V to GND. A 0.1uF cap at Vref pin (pin6)
is recommended.
The MT91610 operating current mode is
recommended to be between 20mA and 30mA. The
device will automatically switch to voltage hold over
mode should an unexpected long loop situation
occur for a given programmed loop current. The
lowest operational current should be 16mA with
VBAT set at -48V. A typical Operating Current versus
Loop Resistance with VBAT at -48V is shown in
Figure 7.
MT91610
Balanced Ringing & Automatic Ring
Tripping
Balanced Ringing is applied to the line by setting the
RC to +5V (pin 25) and connecting ringing signal
(20Hz) to RV (pin 35) as shown in Figure 4. A
1.2Vrms input will give approximately about 60Vrms
output across Tip and Ring, sufficient for short loop
SLIC application. The SLIC is capable of detecting
an Off Hook condition during ringing by filtering out
the large A.C. component. A 0.47uF cap should be
connected to pin CP6 (pin 29) to form such filter.
This filter allows a true Off Hook condition to be
monitored at pin SHK (pin 33). When an Off Hook
condition is detected by the SLIC, it will remove the
20Hz AC ringing voltage and revert to constant
current mode. The local controller will, however, still
need to deselect RC (set it to 0V).
The MT91610 supports short burst of ringing
cadence. A deglitching input (CP7) is provided to
ensure that the SHK pin is glitch free during the
assertion and de-assertion of RC. A 33nF cap
should be connected at this pin to GND.
A
positive voltage source is required to be
connected to the pin DCRI (Figure 5) for normal
Ringing generation. The SLIC can perform ringing
even with the DCRI input connected to 0V. However,
it does require the VBAT to be lower than -48V (ie at
-53V or lower) and the 20Hz AC input should be a
square wave at 2Vrms.
UD & Line Drivers Overcurrent
Protection
The Line Drivers control the external Battery Feed
circuit which provide power to the line and allows bi-
directional audio transmission.
The loop supervision circuitry provides bias to the
line drivers to feed a constant current. Overcurrent
protection is done by the following steps:
(A) External bipolar transistors to limit the current of
the NPN drivers to 50mA (Figure 5).
(B) The local controller should monitor the
Unbalance Detection output (UD) for any extended
period of assertion (>5 seconds). In such case the
controller should power down the device by asserting
the PD pin, and polls the device every 5 seconds.
The UD output can be used to support GND START
LOOP in a PaBX operation.
Please note that this UD output should be
disregarded and masked out if RC pin is active (ie
set to +5V).
Line Reversal
The MT91610 can deliver Line Reversal, which is
required in operation such as ANI, by simply setting
LR (pin 7) to +5V. The device transmission
parameters will cease during the reversal. The LR
(pin 7) should be set to 0V for all normal loop
operations.
Power Down And Wake Up
The MT91610 should normally be powered down to
conserve energy by setting the PD pin to +5V. The
SHK pin will be asserted if the equipment side (2
wire) goes off hook. The local controller should then
restore power to the SLIC for normal operations by
setting the PD pin to 0V.
Please note that there will be a short break (about
80ms) in the assertion time of SHK due to the time
required for the loop to power up and loop current to
flow. The local controller should be able to mask out
this time fairly easily.
5
Powering Up / Down Sequence
AGND is always connected
Powering Up: +5V, -5V, VBAT
PD to +5V for 100ms; PD to 0V
Powering Down: VBAT, -5V, +5V
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