®
·
Designed for Short-Range Wireless Data Communications
·
Supports RF Data Transmission Rates Up to 115.2 kbps
·
3 V, Low Current Operation plus Sleep Mode
·
Stable, Easy to Use, Low External Parts Count
The TR1000 hybrid transceiver is ideal for short-range wireless data applications where robust
operation, small size, low power consumption and low cost are required. The TR1000 employs
RFM’s amplifier-sequenced hybrid (ASH) architecture to achieve this unique blend of character-
istics. All critical RF functions are contained in the hybrid, simplifying and speeding design-in.
The receiver section of the TR1000 is sensitive and stable. A wide dynamic range log detector,
in combination with digital AGC and a compound data slicer, provide robust performance in the
presence of on-channel interference or noise. Two stages of SAW filtering provide excellent re-
ceiver out-of-band rejection. The transmitter includes provisions for both on-off keyed (OOK)
and amplitude-shift keyed (ASK) modulation. The transmitter employs SAW filtering to suppress
output harmonics, facilitating compliance with FCC 15.249 and similar regulations.
TR1000
916.50 MHz
Hybrid
Transceiver
Absolute Maximum Ratings
Rating
Power Supply and All Input/Output Pins
Non-Operating Case Temperature
Soldering Temperature (10 seconds)
Value
-0.3 to +4.0
-50 to +100
230
Units
V
o
o
C
C
Electrical Characteristics, 2.4 kbps On-Off Keyed, Low-Current RX Mode
Characteristic
Operating Frequency
Modulation Type
Data Rate
Receiver Performance (OOK @ 2.4 kbps)
Input Current, 3 Vdc Supply
Input Signal for 10
-4
BER, 25
°
C
Rejection, ±30 MHz
Transmitter Performance (OOK @ 2.4 kbps)
Peak Input Current, 3 Vdc Supply
Peak Output Power
Turn On/Turn Off Time
Sleep to Receive Switch Time (100 ms sleep, -85 dBm signal)
Sleep Mode Current
Transmit to Receive Switch Time (100 ms transmit, -85 dBm signal)
Receive to Transmit Switch Time
Power Supply Voltage Range
Operating Ambient Temperature
I
TP
P
O
t
ON
/t
OFF
t
SR
I
S
t
TOR
t
RTO
V
CC
T
A
2.7
-40
3
200
12
3.5
+85
3
200
5
0.75
12/6
12
mA
mW
µs
µs
µA
µs
µs
Vdc
o
Sym
f
O
Notes
Minimum
916.30
Typical
Maximum
916.70
Units
MHz
OOK
2.4
kbps
I
R
1
R
REJ
55
-98
1.8
mA
dBm
dB
C
1
Electrical Characteristics, 19.2 kbps On-Off Keyed, High-Sensitivity RX Mode
Characteristic
Operating Frequency
Modulation Type
Data Rate
Receiver Performance (OOK @ 19.2 kbps)
Input Current, 3 Vdc Supply
Input Signal for 10
-4
BER, 25
°
C
Rejection, ±30 MHz
Transmitter Performance (OOK @ 19.2 kbps)
Peak Input Current, 3 Vdc Supply
Peak Output Power
Turn On/Turn Off Time
Sleep to Receive Switch Time (90 ms sleep, -80 dBm signal)
Sleep Mode Current
Transmit to Receive Switch Time (90 ms transmit, -80 dBm signal)
Receive to Transmit Switch Time
Power Supply Voltage Range
Operating Ambient Temperature
I
TP
P
O
t
ON
/t
OFF
t
SR
I
S
t
TOR
t
RTO
V
CC
T
A
2.7
-40
3
20
12
3.5
+85
3
20
5
0.75
12/6
12
mA
mW
µs
µs
µA
µs
µs
Vdc
o
Sym
f
O
Notes
Minimum
916.30
Typical
Maximum
916.70
Units
MHz
OOK
19.2
kbps
I
R
1
R
REJ
55
-95
4.5
mA
dBm
dB
C
Electrical Characteristics, 115.2 kbps Amplitude-Shift Keyed, High-Sensitivity RX Mode
Characteristic
Operating Frequency
Modulation Type
Data Rate
Receiver Performance (ASK @ 115.2 kbps)
Input Current, 3 Vdc Supply
Input Signal for 10
-4
BER, 25
°
C
Rejection, ±30 MHz
Transmitter Performance (ASK @ 115.2 kbps)
Peak Input Current, 3 Vdc Supply
Peak Output Power
Output Rise/Fall Time
Sleep to Receive Switch Time (15 ms sleep, -76 dBm signal)
Sleep Mode Current
Transmit to Receive Switch Time (15 ms transmit, -76 dBm signal)
Receive to Transmit Switch Time
Power Supply Voltage Range
Operating Ambient Temperature
I
TP
P
O
t
TR
/t
TF
t
SR
I
S
t
TAR
t
RTA
V
CC
T
A
2.7
-40
3
20
12
3.5
+85
3
20
5
0.75
1.1/1.1
12
mA
mW
µs
µs
µA
µs
µs
Vdc
o
Sym
f
O
Notes
Minimum
916.30
Typical
Maximum
916.70
Units
MHz
ASK
115.2
kbps
I
R
2
R
REJ
55
-85
4.8
mA
dBm
dB
C
2
A S H T r a n s c e iv e r A p p lic a tio n C ir c u it
O O K C o n fig u r a tio n
+ 3
V D C
R
C
R F B 2
R F B
A S H T r a n s c e iv e r A p p lic a tio n C ir c u it
A S K C o n fig u r a tio n
+ 3
V D C
R
R F B
C
+
D C B
C
R F B 2
C
+
D C B
T /R
R
P W
R
R
P R
T H 1
T /R /S
1 3
T H L D
1
1 2
T H L D
2
R R E F
G N D 2
L P F
A D J
9
1 9
1 8
C N T
R L 0
1 7
C N T
R L 1
1 6
V C C
2
R
P W
R
R
P R
T H 1
1 9
1 8
C N T
R L 0
1 7
C N T
R L 1
1 6
V C C
2
1 5
P
W ID T H
1 4
P
R A T E
1 5
P
W ID T H
1 4
P
R A T E
1 3
T H L D
1
1 2
T H L D
2
R R E F
G N D 2
L P F
A D J
9
R
T H 2
L
A T
2 0
G N D
3
R F IO
G N D 1
V C C
1
1
2
L
1 1
A T
T O P V IE W
A G C
C A P
3
P K
D E T
4
B B
O U T
5
C M P
IN
6
R X
D A T A
7
T X
M O D
8
R
2 0
R E F
G N D
3
R F IO
G N D 1
V C C
1
1
2
T O P V IE W
A G C
C A P
3
R F B
1 1
R
R E F
L
E S D
1 0
L
E S D
P K
D E T
4
B B
O U T
5
C M P
IN
6
R X
D A T A
7
T X
M O D
8
1 0
L
+ 3
V D C
R F B
R
C
C
R F B 1
B B O
L P F
L
R
C
B B O
L P F
R
T X M
R
T X M
C
M o d u la tio n In p u t
D a ta O u tp u t
R F B 1
+ 3
V D C
C
A G C
C
P K D
M o d u la tio n In p u t
D a ta O u tp u t
Transceiver Set-Up, 3.0 Vdc, -40 to +85
0
C
Item
Nominal NRZ Data Rate
Minimum Signal Pulse
Maximum Signal Pulse
AGCCAP Capacitor
PKDET Capacitor
BBOUT Capacitor
TXMOD Resistor
LPFADJ Resistor
RREF Resistor
THLD2 Resistor
THLD1 Resistor
PRATE Resistor
PWIDTH Resistor
RF Bypass Resistor
DC Bypass Capacitor
RF Bypass Capacitor 1
RF Bypass Capacitor 2
RF Bypass Bead
Series Tuning Inductor
Shunt Tuning/ESD Inductor
Symbol
DR
NOM
SP
MIN
SP
MAX
C
AGC
C
PKD
C
BBO
R
TXM
R
LPF
R
REF
R
TH2
R
TH1
R
PR
R
PW
R
RFB
C
DCB
C
RFB1
C
RFB2
L
RFB
L
AT
L
ESD
OOK
2.4
416.67
1666.68
-
-
0.1
8.2
240
100
-
10
1100
270 to GND
100
10
27
100
Fair-Rite
10
100
OOK
19.2
52.08
208.32
-
-
0.015
8.2
30
100
-
27
330
270 to GND
100
10
27
100
Fair-Rite
10
100
ASK
115.2
8.68
34.72
2200
0.001
0.0027
8.2
12
100
100
100
160
1000 to Vcc
100
10
27
100
Fair-Rite
10
100
Units
kbps
µs
µs
pF
µF
µF
K
K
K
K
K
K
K
ohm
µF
pF
pF
vendor
nH
nH
Notes
see pages 1 & 2
single bit
4 bits of
same value
±10% ceramic
±10% ceramic
±10% ceramic
±5%, for 0.25 mW output
±5%
±1%
±1%, for 6 dB below peak
±1%, typical values
±5%
±5%
±5%
tantalum
±5% NPO
±5% NPO
2506033017YO or equivalent
50 ohm antenna
50 ohm antenna
CAUTION: Electrostatic Sensitive Device. Observe precautions when handling.
Notes:
1. OOK BER measured with no DS1 threshold (DS2 disabled), and data encoded for DC-balance with a run length limited to 4 bit periods.
2. ASK BER measured with a 25 mV DS1 threshold, DS2 threshold 6 dB below peak, and data encoded for DC-balance with a run length
limited to 4 bit periods.
3. Transmit/sleep to receive recovery time is for the period and signal level indicated, -40 to 60
o
C. Recovery time will increase at higher
temperatures, for longer transmit/sleep intervals and lower signal levels. See the
ASH Transceiver Designer’s Guide, Appendix D.
3
ASH Transceiver Theory of Operation
Introduction
RFM’s amplifier-sequenced hybrid (ASH) transceiver is specifically
designed for short-range wireless data communication applications.
The transceiver provides robust operation, very small size, low
power consumption and low implementation cost. All critical RF
functions are contained in the hybrid, simplifying and speeding de-
sign-in. The ASH transceiver can be readily configured to support a
wide range of data rates and protocol requirements. The transceiver
features excellent suppression of transmitter harmonics and virtually
no RF emissions when receiving, making it easy to certify to short-
range (unlicensed) radio regulations.
Amplifier-Sequenced Receiver Operation
The ASH transceiver’s unique feature set is made possible by its
system architecture. The heart of the transceiver is the amplifier-
sequenced receiver section, which provides over 90 dB of stable RF
and detector gain without any special shielding or decoupling provi-
sions. Stability is achieved by distributing the total RF gain over
time.
This is in contrast to a superheterodyne receiver, which
achieves stability by distributing total RF gain over multiple frequen-
cies.
Figure 1 shows the basic block diagram and timing cycle for an am-
plifier-sequenced receiver. Note that the bias to RF amplifiers RFA1
and RFA2 are independently controlled by a pulse generator, and
that the two amplifiers are coupled by a surface acoustic wave
(SAW) delay line, which has a typical delay of 0.5 µs.
An incoming RF signal is first filtered by a narrow-band SAW filter,
and is then applied to RFA1. The pulse generator turns RFA1 ON
for 0.5 µs. The amplified signal from RFA1 emerges from the SAW
delay line at the input to RFA2. RFA1 is now switched OFF and
RFA2 is switched ON for 0.55 µs, amplifying the RF signal further.
The ON time for RFA2 is usually set at 1.1 times the ON time for
RFA1, as the filtering effect of the SAW delay line stretches the sig-
nal pulse from RFA1 somewhat. As shown in the timing diagram,
RFA1 and RFA2 are never on at the same time, assuring excellent
receiver stability. Note that the narrow-band SAW filter eliminates
sampling sideband responses outside of the receiver passband, and
the SAW filter and delay line act together to provide very high re-
ceiver ultimate rejection.
Amplifier-sequenced receiver operation has several interesting char-
acteristics that can be exploited in system design. The RF amplifiers
in an amplifier-sequenced receiver can be turned on and off almost
instantly, allowing for very quick power-down (sleep) and wake-up
times. Also, both RF amplifiers can be off between ON sequences
to trade-off receiver noise figure for lower average current consump-
tion. The effect on noise figure can be modeled as if RFA1 is on
continuously, with an attenuator placed in front of it with a loss
equivalent to 10*log
10
(RFA1 duty factor), where the duty factor is the
average amount of time RFA1 is ON (up to 50%). Since an
amplifier-sequenced receiver is inherently a sampling receiver, the
overall cycle time between the start of one RFA1 ON sequence and
A S H R e c e iv e r B lo c k D ia g r a m
A n te n n a
& T im in g C y c le
S A W
F ilte r
R F A 1
P 1
S A W
D e la y L in e
R F A 2
P 2
D e te c to r &
L o w -P a s s
F ilte r
D a ta
O u t
P u ls e
G e n e ra to r
R F In p u t
t
P
P 1
R F A 1 O u t
W 1
R F D a ta P u ls e
t
P
t
P
R C
R I
D e la y L in e
O u t
t
P
P 2
W 2
Figure 1
4
A S H T r a n s c e iv e r B lo c k D ia g r a m
T X
IN
R
T X M O D
8
C N
C N
T R L 1 T R L 0
T X M
1 7
1 8
P o w e r D o w n
C o n tro l
M o d u la tio n
& B ia s C o n tr o l
V C C
V C C
G N D
G N D
G N D
R R E
C M P
1 :
2 :
1 :
2 :
3 :
F :
IN :
P in
P in
P in
P in
P in
P in
P in
2
1 6
1
1 0
1 9
1 1
6
B B O U T
A n te n n a
R F IO
2 0
T u n in g
T u n in g /E S D
T X A 2
T X A 1
L o g
S A W
C R F ilte r
R F A 1
S A W
D e la y L in e
R F A 2
D e te c to r
L o w -P a s s
F ilte r
L P F A D J
9
R
L P F
B B
5
C
6
B B O
P e a k
D e te c to r
P K D E T
4
C
P K D
R e f
D S 2
d B B e lo w
P e a k T h ld
A N D
7
R X D A T A
A G C S e t
G a in S e le c t
P u ls e G e n e r a to r
& R F A m p B ia s
P R A T E
1 4
R
P R
A G C
R e f
A G C
C o n tro l
A G C C A P
3
C
A G C R e s e t
1 3
R
T H 1
D S 1
T h ld
T h r e s h o ld
C o n tro l
1 5
R
P W ID T H
P W
A G C
T H L D 1
1 1
R
R
R E F
T H 2
1 2
T H L D 2
Figure 2
the start of the next RFA1 ON sequence should be set to sample
the narrowest RF data pulse at least 10 times. Otherwise, significant
edge jitter will be added to the detected data pulse.
ASH Transceiver Block Diagram
Figure 2 is the general block diagram of the ASH transceiver.
Please refer to Figure 2 for the following discussions.
Antenna Port
The only external RF components needed for the transceiver are
the antenna and its matching components. Antennas presenting an
impedance in the range of 35 to 72 ohms resistive can be satisfacto-
rily matched to the RFIO pin with a series matching coil and a shunt
matching/ESD protection coil. Other antenna impedances can be
matched using two or three components. For some impedances,
two inductors and capacitor will be required. A DC path from RFIO
to ground is required for ESD protection.
Receiver Chain
The output of the SAW filter drives amplifier RFA1. This amplifier in-
cludes provisions for detecting the onset of saturation (AGC Set),
and for switching between 35 dB of gain and 5 dB of gain (Gain Se-
lect). AGC Set is an input to the AGC Control function, and Gain Se-
lect is the AGC Control function output. ON/OFF control to RFA1
(and RFA2) is generated by the Pulse Generator & RF Amp Bias
function. The output of RFA1 drives the SAW delay line, which has
a nominal delay of 0.5 µs.
The second amplifier, RFA2, provides 51 dB of gain below satura-
tion. The output of RFA2 drives a full-wave detector with 19 dB of
threshold gain. The onset of saturation in each section of RFA2 is
detected and summed to provide a logarithmic response. This is
added to the output of the full-wave detector to produce an overall
detector response that is square law for low signal levels, and tran-
sitions into a log response for high signal levels. This combination
provides excellent threshold sensitivity and more than 70 dB of
detector dynamic range. In combination with the 30 dB of AGC
range in RFA1, more than 100 dB of receiver dynamic range is
achieved.
The detector output drives a gyrator filter. The filter provides a
three-pole, 0.05 degree equiripple low-pass response with excellent
group delay flatness and minimal pulse ringing. The 3 dB bandwidth
of the filter can be set from 4.5 kHz to 1.8 MHz with an external re-
sistor.
The filter is followed by a base-band amplifier which boosts the de-
tected signal to the BBOUT pin. When the receiver RF amplifiers
are operating at a 50%-50% duty cycle, the BBOUT signal changes
about 10 mV/dB, with a peak-to-peak signal level of up to 685 mV.
For lower duty cycles, the mV/dB slope and peak-to-peak signal
level are proportionately less. The detected signal is riding on a
1.1 Vdc level that varies somewhat with supply voltage, tempera-
ture, etc. BBOUT is coupled to the CMPIN pin or to an external data
recovery process (DSP, etc.) by a series capacitor. The correct
value of the series capacitor depends on data rate, data run length,
and other factors as discussed in the
ASH Transceiver Designer’s
Guide.
When an external data recovery process is used with AGC, BBOUT
must be coupled to the external data recovery process and CMPIN
by separate series coupling capacitors. The AGC reset function is
driven by the signal applied to CMPIN.
When the transceiver is placed in power-down (sleep) or in a trans-
mit mode, the output impedance of BBOUT becomes very high. This
feature helps preserve the charge on the coupling capacitor to mini-
mize data slicer stabilization time when the transceiver switches
back to the receive mode.
Data Slicers
The CMPIN pin drives two data slicers, which convert the analog
signal from BBOUT back into a digital stream. The best data slicer
choice depends on the system operating parameters. Data slicer
DS1 is a capacitively-coupled comparator with provisions for an ad-
justable threshold. DS1 provides the best performance at low
5
模拟与混合信号
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
