R
EM MICROELECTRONIC -
MARIN SA
EM6620
Ultra Low Power Microcontroller with 4x8 LCD Driver
Features
•
Low Power
- 2.1 µA active mode, LCD On
- 0.5 µA standby mode, LCD Off
- 0.1 µA sleep mode
@ 1.5V, 32kHz, 25°C
Low Voltage
- 1.2 to 3.6 V
SVLD - metal mask programmable (2.0V)
ROM
- 1280
×
16 bits
RAM
- 64
×
4 bits
2 clocks per instruction cycle
72 basic instructions
Oscillation supervisor
Timer watchdog (2 sec)
Max. 8 inputs ; port A, port B
max. 4 outputs ; port B
LCD 8 segments, 3 or 4 times multiplexed
Universal 10-bit counter, PWM, event counter
Prescaler down to 1 Hz (crystal = 32 KHz)
1/1000 sec, 12 bit binary coded decimal counter
with hard or software start/stop function
Frequency output 1Hz, 2048 Hz, 32 KHz, PWM
7 internal interrupt sources (BCD counter,
2×10-bit counter, 3× prescaler, SVLD)
5 external interrupt sources (port A, compare)
Figure 1. Architecture
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Description
The EM6620 is an advanced single chip CMOS 4-
bit microcontroller. It contains ROM, RAM, power
on reset, watchdog timer, oscillation detection
circuit, 10 bit up/down counter, Millisecond counter,
prescaler, voltage level detector (SVLD), compare
input, frequency output, LCD driver and several
clock functions. The low voltage feature and low
power consumption make it the most suitable
controller for battery, stand alone and mobile
equipment. The EM6620 is manufactured using EM
Microeletronic’s Advanced Low Power (ALP)
CMOS Process.
Figure 2. Pin Configuration
Typical Applications
•
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Timing device
Medical applications
Domestic appliance
Timer / sports timing devices
Safety and security devices
Automotive controls with display
Measurement equipment
Interactive system with display
Bicycle computers
Copyright
©
2005, EM Microelectronic-Marin SA
1
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EM6620
EM6620 at a glance
•
Power Supply
- Low voltage low power architecture
including internal voltage regulator
- 1.2 ... 3.6 V battery voltage
- 2.1 µA in active mode (Xtal, LCD on, 25°C)
- 0.5 µA in standby mode (Xtal, LCD off, 25°C)
- 0.1 µA in sleep mode (25°C)
- 32 KHz Oscillator
•
Prescaler
- 15 stage system clock divider down to 1Hz
- 3 Interrupt requests; 1Hz, 32Hz or 8Hz, Blink
- Prescaler reset (4kHz to 1Hz)
•
4-Bit Bi-directional Port B
-
All different functions bit-wise selectable
•
•
•
RAM
ROM
CPU
- 64 x 4 bit, direct addressable
- 1280 x 16 bits, metal mask programmable
- Direct input read on the port terminals
- Data output latches
- CMOS or Nch. open drain outputs
- Pull-down or pull-up selectable
- Weak pull-up in Nch. open drain mode
- Selectable PWM, 32kHz, 1kHz and 1Hz output
- Dynamic Input Comparator on PB[0] (SVLD level)
•
Voltage Level Detector
- Mask selectable level, default 2.0V
- Busy flag during measure
- Interrupt request at end of measure
•
- 4 bit RISC architecture
- 2 clock cycles per instruction
- 72 basic instructions
•
Main Operating Modes and Resets
- Active Mode (CPU is running)
- Standby Mode (CPU in halt)
- Sleep Mode (no clock, reset state)
- Initial reset on power on (POR)
- Watchdog reset (logic and oscillation watchdogs)
- Reset with input combination on port A (register
selectable)
•
Liquid Crystal Display Driver (LCD)
- 8 segments 3 or 4 times multiplexed
- Internal or external voltage multiplier
- Free segment allocation architecture
(metal 2 mask)
- LCD switch off for power save
•
4-Bit Input Port A
- Direct input read on the port terminals
- Debouncer function available on all inputs
- Interrupt request on positive or negative edge
- Pull-up or pull-down or none selectable by
register
- Test variables (software) for conditional jumps
- PA[0] and PA[3] are inputs for the event counter
- PA[3] is Start/Stop input for the millisecond
counter
- Reset with input combination (register selectable)
10-Bit Universal Counter
- 10, 8, 6 or 4 bit up/down counting
- Parallel load
- Event counting (PA[0] or PA[3])
- 8 different input clocks-
- Full 10 bit or limited (8, 6, 4 bit) compare function
- 2 interrupt requests (on compare and on 0)
- Hi-frequency input on PA[3] and PA[0]
- Pulse width modulation (PWM) output
•
Millisecond Counter
- 3 digits binary coded decimal counter (12 bits)
- PA[3] signal pulse width and period measurement
- Internal 1000 Hz clock generation
- Hardware or software controlled start stop mode
- Interrupt request on either 1/10 Sec or 1Sec
•
Interrupt Controller
- 5 external and 7 internal interrupt request sources
- Each interrupt request individually maskable
- Each interrupt flag individually resettable
- Automatic reset of each interrupt request register
after read
- General interrupt request to CPU can be disabled
- Automatic enabling of general interrupt request
flag when going into HALT mode
Copyright
©
2005, EM Microelectronic-Marin SA
2
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EM6620
Table of Contents
Features ________________________________ 1
Description ______________________________ 1
TYPICAL applications ______________________ 1
EM6620 at a glance _______________________ 2
PIN DESCRIPTION FOR EM6620 _______ 4
1.
2.
2.1
2.2
2.3
3.
OPERATING MODES ________________ 6
ACTIVE M
ODE
__________________________ 6
STANDBY M
ODE
________________________ 6
SLEEP M
ODE
___________________________ 6
POWER SUPPLY____________________ 7
8.3
8.4
8.5
9.
9.1
10.
10.1
11.
12.
12.1
12.2
12.3
12.4
13.
14.
15.
MSC-M
ODES
__________________________ 28
M
ODE SELECTION
_______________________ 28
M
ILLISECOND
C
OUNTER
R
EGISTERS
_________ 30
INTERRUPT CONTROLLER __________ 31
I
NTERRUPT CONTROL REGISTERS
___________ 32
SUPPLY VOLTAGE LEVEL DETECTOR_ 33
SVLD R
EGISTER
________________________ 33
RAM _____________________________ 34
LCD DRIVER_______________________ 35
LCD C
ONTROL
_________________________ 36
LCD
ADDRESSING
_______________________ 36
F
REE SEGMENT ALLOCATION
______________ 37
LCD R
EGISTERS
________________________ 37
PERIPHERAL MEMORY MAP _________ 39
OPTION REGISTER MEMORY MAP ____ 42
ACTIVE SUPPLY CURRENT TEST _____ 43
4.
RESET ____________________________ 8
4.1
O
SCILLATION
D
ETECTION
C
IRCUIT
___________ 9
4.2
I
NPUT
P
ORT
A R
ESET
______________________ 9
4.3
D
IGITAL
W
ATCHDOG
T
IMER
R
ESET
__________ 10
4.4
CPU S
TATE AFTER
R
ESET
_________________ 10
5.
OSCILLATOR AND PRESCALER _____ 11
5.1
O
SCILLATOR
___________________________ 11
5.2
P
RESCALER
____________________________ 11
6.
INPUT AND OUTPUT PORTS_________ 13
6.1
P
ORTS OVERVIEW
_______________________ 13
6.2
P
ORT
A _______________________________ 14
6.2.1
IRQ on Port A ______________________ 14
6.2.2
Pull-up/down_______________________ 15
6.2.3
Software test variables _______________ 15
6.2.4
Port A for 10-Bit Counter and MSC _____ 15
6.3
P
ORT
A
REGISTERS
______________________ 15
6.4
P
ORT
B _______________________________ 17
6.4.1
Input / Output Mode _________________ 17
6.4.2
Pull-up/Down ______________________ 18
6.4.3
CMOS / NCH. Open Drain Output ______ 18
6.4.4
PWM and Frequency output ___________ 19
6.5
PB[0] D
YNAMIC
I
NPUT
C
OMPARATOR
________ 19
6.6
P
ORT
B
REGISTERS
_______________________ 20
7.
10-BIT COUNTER __________________ 21
7.1
F
ULL AND
L
IMITED
B
IT
C
OUNTING
__________ 21
7.2
F
REQUENCY
S
ELECT AND
U
P
/D
OWN
C
OUNTING
22
7.3
E
VENT
C
OUNTING
_______________________ 23
7.4
C
OMPARE
F
UNCTION
_____________________ 23
7.5
P
ULSE
W
IDTH
M
ODULATION
(PWM) ________ 23
7.5.1
How the PWM Generator works. _______ 24
7.5.2
PWM Characteristics ________________ 24
7.6
C
OUNTER
S
ETUP
________________________ 25
7.7
10-
BIT
C
OUNTER
R
EGISTERS
_______________ 25
8.
MILLISECOND COUNTER ___________ 27
8.1
PA[3] I
NPUT FOR
MSC ___________________ 27
8.2
IRQ
FROM
MSC_________________________ 27
16.
MASK OPTIONS ____________________ 44
16.1 I
NPUT
/ O
UTPUT
P
ORTS
___________________ 44
16.1.1 Port A Metal Options ________________ 44
16.1.2 Port B Metal Options ________________ 45
16.1.3 Voltage Regulator Option ____________ 46
16.1.4 SVLD and Input Comp Level Option ____ 46
16.1.5 Debouncer frequency Option __________ 46
16.1.6 User defined LCD Segment allocation___ 46
17.
TEMP. AND VOLTAGE BEHAVIORS ___ 47
17.1 IDD C
URRENT
(
TYPICAL
) _________________ 47
17.2 P
ULL
-
DOWN
R
ESISTANCE
(
TYPICAL
)_________ 47
17.3 P
ULL
-
UP
R
ESISTANCE
(
TYPICAL
) ___________ 48
17.4 O
UTPUT CURRENTS
(
TYPICAL
) _____________ 48
18.
EM6620 ELECTRICAL SPECIFICATIONS 49
18.1 A
BSOLUTE MAXIMUM RATINGS
_____________ 49
18.2 H
ANDLING
P
ROCEDURES
_________________ 49
18.3 S
TANDARD
O
PERATING
C
ONDITIONS
________ 49
18.4 DC
CHARACTERISTICS
- P
OWER
S
UPPLY
______ 49
18.5 SVLD
AND
I
NPUT
C
OMPARATOR
___________ 50
18.6 O
SCILLATOR
___________________________ 50
18.7 DC
CHARACTERISTICS
- I/O P
INS
___________ 51
18.8 LCD S
EG
[8:1] O
UTPUTS
__________________ 52
18.9 LCD C
OM
[4:1] O
UTPUTS
_________________ 52
18.10
DC O
UTPUT
C
OMPONENT
_______________ 52
18.11
LCD
VOLTAGE MULTIPLIER
_____________ 52
19.
PAD LOCATION DIAGRAM ___________ 53
20.
20.1
20.2
20.3
PACKAGE & ORDERING INFORMATION 54
O
RDERING
I
NFORMATION
_________________ 56
P
ACKAGE
M
ARKING
_____________________ 56
C
USTOMER
M
ARKING
____________________ 56
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©
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EM6620
1. Pin Description for EM6620
Chip QFP DIL
44
40
1
13
7
2
14
8
3
15
9
4
16
10
5
18
11
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
19
20
21
25
26
27
28
29
30
31
32
33
35
36
37
38
39
40
41
12
13
14
17
18
19
20
21
22
23
24
25
27
28
29
30
31
32
33
QFP
32
9
10
11
12
13
14
15
16
17
18
19
nc
20
21
22
23
24
25
26
27
28
29
30
31
Signal Name
C2B
C2A
C1B
C1A
VL1
VL2
VL3
COM[4]
COM[3]
COM[2]
COM[1]
SEG[8]
SEG[7]
SEG[6]
SEG[5]
SEG[4]
SEG[3]
SEG[2]
SEG[1]
Test
PB[0]
PB[1]
PB[2]
PB[3]
Function
Voltage multiplier
Voltage multiplier
Voltage multiplier
Voltage multiplier
Voltage multiplier level 1
Voltage multiplier level 2
Voltage multiplier level 3
LCD back plane 4
LCD back plane 3
LCD back plane 2
LCD back plane 1
LCD segment 8
LCD segment 7
LCD segment 6
LCD segment 5
LCD segment 4
LCD segment 3
LCD segment 2
LCD segment 1
Input test terminal
Internal pull-down 15k
Input/output, open drain
port B terminal 0
Input/output, open drain
port B terminal 1
Input/output, open drain
port B terminal 2
Input/output, open drain
port B terminal 3
Input port A terminal 0
Input port A terminal 1
Input port A terminal 2
Input port A terminal 3
Remarks
Not needed if ext. supply
Not needed if ext. supply
Not needed if ext. supply
Not needed if ext. supply
LCD level 1 input, if external supply
selected
LCD level 2 input, if external supply
selected
LCD level 3 input, if external supply
selected
Not used if 3 times multiplex
selected
Not bonded for QFP 32
For EM tests only, GND 0 ! except
when needed for MFP programming
Port B data[0] I/O or
dynamic input comparator input
Port B data[1] I/O or
ck[12] output
Port B data[2] I/O or
ck[1] output
Port B data[3] I/O or
PWM output
Testvar 1
Event counter
Testvar 2
Testvar 3
Event counter
MSC start/stop control
MFP Connection
Connect to minimum 100nF,
MFP Connection
32kHz crystal, MFP Connection
32kHz crystal, MFP Connection
Reference terminal, MFP Connection
25
26
27
28
43
1
2
3
35
36
37
38
32
1
2
3
PA[0]
PA[1]
PA[2]
PA[3]
29
30
31
32
33
5
6
8
10
11
39
40
1
3
5
4
5
6
7
8
VBAT=VDD
Vreg
Qout / Osc2
Qin / Osc1
VSS
Positive power supply
Internal voltage regulator
Crystal terminal
Crystal terminal
Negative power supply
* gray shaded : terminals needed for MFP programming connections (VDD, VregLogic, Qin, Qout, Test, VSS).
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EM6620
Figure 3. Typical configuration
L C D D is p la y
C1
C1
C1
c rys ta l
Q IN
QOUT
a ll C a p a c ito rs 1 0 0 n F
VL1
VL2
VL3
C O M [4 :1 ]
S E G [8 :1 ]
C2
C2
C1A
C1B
C2A
C2B
EM 6620
V D D (V B A T )
V re g
T e st
P o rt A
VSS
P o rt B
C3
C4
Copyright
©
2005, EM Microelectronic-Marin SA
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