LSI/CSI
UL
®
RED SERIES
(631) 271-0400 FAX (631) 271-0405
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
A3800
AC LINE FREQUENCY DIVIDERS
July 2000
RED SERIES
RED 5/6
Divide by 5 or 6
RED 50/60
Divide by 50 or 60
RED 100/120
Divide by 100 or 120
RED 300/360
Divide by 300 or 360
RED 500/600
Divide by 500 or 600
RED 3000/3600
Divide by 3000 or 3600
FEATURES:
• Clock input pulse shaper accepts 50Hz/60Hz
sine wave directly
• Fully static counter operation
• +4.5V to +15V operation (V
DD
- V
SS
)
• Low power dissipation
• High noise immunity
• Reset
• Input Enable
• 50Hz/60Hz division select input
• Output low power TTL compatible at +4.5V operation
• Square Wave Output (except for ÷ 5)
• RED x/y (DIP); RED x/y-S (SOIC) See Figure 1
APPLICATION:
Time base generator from either 50Hz or 60Hz line
frequency to produce:
10 pulses per second
1 pulse per second
1 pulse per 2 seconds
1 pulse per .1 minute
1 pulse per 10 seconds
1 pulse per minute
(RED 5/6)
(RED 50/60)
(RED 100/120)
(RED 300/360)
(RED 500/600)
(RED 3000/3600)
PIN ASSIGNMENT - TOP VIEW
LSI
OUTPUT
1
8
V
DD
(V+)
RESET
2
7
DIVISION SELECT
V
SS
(-V)
3
6
ENABLE
NC
4
5
CLOCK INPUT
FIGURE 1
MARKING AS FOLLOWS:
PART
MARKING
RED 5/6
RED 50/60
RED 100/120
RED 300/360
RED 500/600
RED 3000/3600
RED 6
RED 60
RED 120
RED 360
RED 600
RED 3600
DESCRIPTION OF OPERATION:
The counter advances by one on each negative transition of the
input clock pulse as long as the Enable signal is High and the
Reset signal is Low. When the Enable signal is Low the input
clock pulses will be inhibited and the counter will be held at the
state it was in prior to bringing the Enable Low. A High Reset
signal clears the counter to zero count.
Depending on the device used, a Low on the Division Select in-
put will cause a Divide by 6, 60, 120, 360, 600 or 3600. A High
on the Division Select will cause a Divide by 5, 50, 100, 300, 500
or 3000.
All outputs are 50% duty cycle except RED 5, where output is
low for two clocks and high for three clocks.
CLOCK INPUT
If input signals are less than the Vss or greater than V
DD
, a
series input resistor should be used to limit the maximum input
current to 2 mA.
MAXIMUM RATINGS:
PARAMETER
SYMBOL
VALUE
UNIT
Storage Temperature
T
STG
-65 to +150
˚C
Operating Temperature T
A
-40 to +85
˚C
DC Supply Voltage
(V
DD
-Vss)
+18
V
Voltage at any input
V
IN
Vss -.3 to V
DD
+.3 V
ENABLE SIGNAL TIMING
If the Enable signal switches Low during a positive clock phase and
then switches High during a negative clock phase, a false count will
be registered. To prevent this from happening, the Enable signal
should not switch Low during a positive clock phase unless the
switch to High also occurs during a positive clock phase. The
Enable signal should normally be switched during a negative clock
phase.
The information included herein is believed to be
accurate and reliable. However, LSI Computer Systems,
Inc. assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which may
result from its use.
RED-062600-1
ELECTRICAL CHARACTERISTICS:
(TA = 25° unless otherwise specified)
TEST CONDITIONS:
Vss = OV
Output Capacitance Load = 15 pF
Input Rise and Fall times = 20 ns,
except clock Rise and Fall times
Input Capacitance = 5pF max (any input)
V
DD
Min Max
Quiescent Device Current
5V
-
10
10V
-
20
Output Voltage, Low Level
5V
-
0.0
10V
-
0.0
High Level
5V 4.99 -
10V 9.99 -
Clock Input Voltage, Low Level
5V
-
1
10V
-
2
High Level
5V
4
-
10V
8
-
Input Noise Immunity
(except clock)
5V
1.5
-
(Low and High)
10V
3.0
-
Output Drive Current
Full
N Channel Sink Current 4.5V 0.18 -
Temp. (Vout - Vss +.4v)
10V 0.45 -
Range
P Channel Sink Current 4.5V
0.3
-
(Vout - VDD -1)
10V 0.75 -
Clock Rise and Fall Time:
Clock Frequency
V
DD
5V
10V
5V
10V
5V
10V
5V
10V
5V
10V
5V
10V
5V
10V
5V
10V
5V
10V
E
MIN
MAX
No Maximum Limit
No Maximum Limit
DC
600
DC
1200
800
400
-
-
-
-
-
-
800
400
-
-
-
-
-
-
225
150
1500
750
300
150
-
-
1200
600
1400
700
E
UNITS
-
-
kHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input Clock Pulse Width
Units
uA
uA
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
Output Rise and Fall Time
Propagation Delay to Output
Enable Set-up Time
Reset Pulse Width
Reset Removal Time
Reset Propagation Delay
to Output
PULSE SHAPER
E
CL IN 5
E
INPUT CLOCK GENERATOR
CL
CL
R
ENABLE
6
RESET
2
R
DS
VDD
VSS
DIVISION SELECT
+4.5V to +15V
GND
N/C
7
8
3
4
RED 5/6,50/60,
300/360,3000/3600
1
D5/6
DS
1
CL1
CL
3 BIT
JOHNSON
+5/6
CL1
3 BIT
JOHNSON
÷10
CL2
CL2
3 BIT
JOHNSON
÷6
CL3
CL3
D50/60
CL
5 BIT
JOHNSON
÷10
1
D3000/3600
R
RED 100/120
DS
CL2
CL2
1 BIT
÷2
1
D300/360
CL
CL
3 BIT
JOHNSON
+5/6
CL1
CL1
5 BIT
JOHNSON
÷10
1
D100/120
R
RED 500/600
DS
CL
3 BIT
JOHNSON
+5/6
CL1
CL1
5 BIT
JOHNSON
÷10
CL2
CL2
CL
5 BIT
JOHNSON
÷10
1
D500/600
R
FIGURE 2. BLOCK DIAGRAM
RED-062600-2
无线连接
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
