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RED50: 产品描述AC line frequency dividers; 文件大小35KB，共2页; 制造商LSI Computer Systems; 官网地址https://lsicsi.com

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RED50概述

AC line frequency dividers

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LSI/CSI

RED SERIES

(631) 271-0400 FAX (631) 271-0405

LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747

A3800

AC LINE FREQUENCY DIVIDERS

July 2000

RED SERIES

RED 5/6

Divide by 5 or 6

RED 50/60

Divide by 50 or 60

RED 100/120

Divide by 100 or 120

RED 300/360

Divide by 300 or 360

RED 500/600

Divide by 500 or 600

RED 3000/3600

Divide by 3000 or 3600

FEATURES:

• Clock input pulse shaper accepts 50Hz/60Hz

sine wave directly

• Fully static counter operation

• +4.5V to +15V operation (V

- V

)

• Low power dissipation

• High noise immunity

• Reset

• Input Enable

• 50Hz/60Hz division select input

• Output low power TTL compatible at +4.5V operation

• Square Wave Output (except for ÷ 5)

• RED x/y (DIP); RED x/y-S (SOIC) See Figure 1

APPLICATION:

Time base generator from either 50Hz or 60Hz line

frequency to produce:

10 pulses per second

1 pulse per second

1 pulse per 2 seconds

1 pulse per .1 minute

1 pulse per 10 seconds

1 pulse per minute

(RED 5/6)

(RED 50/60)

(RED 100/120)

(RED 300/360)

(RED 500/600)

(RED 3000/3600)

PIN ASSIGNMENT - TOP VIEW

LSI

OUTPUT

(V+)

RESET

DIVISION SELECT

(-V)

ENABLE

CLOCK INPUT

FIGURE 1

MARKING AS FOLLOWS:

PART

MARKING

RED 5/6

RED 50/60

RED 100/120

RED 300/360

RED 500/600

RED 3000/3600

RED 6

RED 60

RED 120

RED 360

RED 600

RED 3600

DESCRIPTION OF OPERATION:

The counter advances by one on each negative transition of the

input clock pulse as long as the Enable signal is High and the

Reset signal is Low. When the Enable signal is Low the input

clock pulses will be inhibited and the counter will be held at the

state it was in prior to bringing the Enable Low. A High Reset

signal clears the counter to zero count.

Depending on the device used, a Low on the Division Select in-

put will cause a Divide by 6, 60, 120, 360, 600 or 3600. A High

on the Division Select will cause a Divide by 5, 50, 100, 300, 500

or 3000.

All outputs are 50% duty cycle except RED 5, where output is

low for two clocks and high for three clocks.

CLOCK INPUT

If input signals are less than the Vss or greater than V

, a

series input resistor should be used to limit the maximum input

current to 2 mA.

MAXIMUM RATINGS:

PARAMETER

SYMBOL

VALUE

UNIT

Storage Temperature

STG

-65 to +150

˚C

Operating Temperature T

-40 to +85

˚C

DC Supply Voltage

-Vss)

+18

Voltage at any input

Vss -.3 to V

+.3 V

ENABLE SIGNAL TIMING

If the Enable signal switches Low during a positive clock phase and

then switches High during a negative clock phase, a false count will

be registered. To prevent this from happening, the Enable signal

should not switch Low during a positive clock phase unless the

switch to High also occurs during a positive clock phase. The

Enable signal should normally be switched during a negative clock

phase.

The information included herein is believed to be

accurate and reliable. However, LSI Computer Systems,

Inc. assumes no responsibilities for inaccuracies, nor for

any infringements of patent rights of others which may

result from its use.

RED-062600-1

RED50相似产品对比

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描述	AC line frequency dividers	AC line frequency dividers	AC line frequency dividers	AC line frequency dividers	AC line frequency dividers	AC line frequency dividers	AC line frequency dividers	AC line frequency dividers

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