DA9316.003
March 23, 2005
MAS9316
16-BIT DAC
· +/- 0.006% DNL and INL
· No Laser Trimming
· Fast Interface Timing
DESCRIPTION
The MAS9316 is a 16-bit, monolithic CMOS, multiplying
digital-to-analog converter (DAC ) designed for direct
microprocessor interface. Its high relative accuracy and
monotonicity is achieved without laser trimming. This is
made possible by the use of highly accurate, low TCR
thin film resistor process and a 4 MSB to 15 decoding
design technique. Hidden errors are eliminated by
testing all the 65536 different input codes.The device
offers advantages like high stability over time and
temperature and low sensitivity to output amplifier offset
combined to excellent performance-to-cost ratio. The
fast input data latches are designed as two 8-bit
segments providing data storage when latched or
transparent operation when unlatched. All digital inputs
have high ESD protection up to 2 kV.
FEATURES
· Linearity TC 0.5 ppm/C
· 2 kV ESD Protection on Digital Inputs
· D4 MSB's Decoded
· All 65536 Codes Tested
· Monolithic CMOS Replacement for SIPEX
· DAC 9331-16-4 and SP9316C-4
· 24-pin PDIP Package
APPLICATION
· Audio applications
· Instrumentation
· uP Controlled systems
BLOCK DIAGRAM
VDD
VREF
.
.
.
BIT16/
LSB
BIT1/
MSB
8-BIT
INPUT
REG.
RFB
16-BIT DAC
8-BIT
INPUT
REG.
IO1
LBE
HBE
DGND
IO2
1
DA9316.003
March 23, 2005
PIN CONFIGURATION
PDIP 24
MAS9316N
BIT12 1
BIT11 2
BIT10 3
BIT9 4
BIT8 5
BIT7 6
BIT6 7
BIT5 8
BIT4 9
BIT3 10
BIT2 11
BIT1/MSB 12
24
23
22
21
20
19
18
17
16
15
14
13
BIT13
BIT14
BIT15
BIT16/LSB
HBE
LBE
DGND
VDD
IO1
IO2
RFB
VREF
PIN DESCRIPTION
Pin name
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
VREF
RFB
IO2
IO1
VDD
DGND
LBE
HBE
BIT 16
BIT 15
BIT 14
PDIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
P
G
I
I
I
I
I
Data bit 12, MSB
Data bit 11
Data bit 10
Data bit 9
Data bit 8
Data bit 7
Data bit 6
Data bit 5
Data bit 4
Data bit 3
Data bit 2
Data bit 1
Reference voltageiInput
Feedback resistor
Current output
Current output
Positive Supply voltage
Digital ground
Low byte enable
High byte enable
Data bit 16, LSB
Data bit 15
Data bit 14
2
Function
DA9316.003
March 23, 2005
PIN DESCRIPTION
Pin name
BIT 13
PDIP
24
I/O
I
Data bit 13
Function
ABSOLUTE MAXIMUM RATINGS
(Ta = 25 C unless otherwise noted)
o
Parameter
Supply Voltage
Vref or RFB to DGND
Output Voltage (Pin 15, 16)
Power Dissipation
Derates above 75
o
C by
Die Junction Temperature
Storage Temperature
Symbol
VDD
Conditions
Min
-0.3
-25
-0.3
Max
+17
+25
VDD+0.3
459
6
+150
Unit
V
V
V
mW
mW/
o
C
o
o
PD
Any package at 75
o
C
C
C
Ts
CAUTION:
1.Do not apply voltages higher than VDD or less than
GND potential on any terminal other than VREF or RFB.
2.The digital inputs are diode clamp protected against
ESD damage. However, permanent damage may occur
on unprotected units from high-energy electrostatic
fields. Use proper anti-static handling procedures.
3.Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation at or above this specification is not implied.
RECOMMEDED OPERATION CONDITIONS
(conditions)
Parameter
Supply Voltage
Supply Current
Supply Current
Power Dissipation
Storage Temperature
Symbol
VDD
IDD
IDD
Pd
Ts
Conditions
Min
+5
Typ
+15
2.0
0.2
Max
+16
4.0
1.0
60
Unit
V
mA
mA
mW
o
All digital inputs VIL or VIH
All digital inputs 0V or 5V
0
+70
C
3
DA9316.003
March 23, 2005
ELECTRICAL CHARACTERISTICS
Static Performance
(test conditions Ta=+25C)
Parameter
Resolution
Integral Nonlinearity
1
Differential Nonlinearity
2
Gain error
Output Leakage Current
at IO1 (pin 16)
Offset Error
Temperature Stability
Symbol
N
INL
DNL
Gfse
Iilk
Conditions
Min
16
Typ
Max
Unit
s
Bits
±0.004
Relative accuracy 13 bits
Monotonic to 14 bits
Measured Using Internal Rfb
DAC
Register Loaded With All 1s
±0.003
±0.1
±0.006
±0.006
±0.2
10
±0.0005
%
%
%
nA
%
(test conditions Ta=+25C)
Parameter
Gain error
Integral Nonlinearity TC
Differential Nonlinearity TC
Reference Input
Symbol
TCTCGFSE
TCINL
TCDNL
Conditions
Min
Typ
±1.0
±0.1
±0.1
Max
±2.0
±0.5
±0.5
Unit
s
pm/C
pm/C
pm/C
(test conditions Ta=+25C)
Parameter
Input Resistance
Voltage Range
3
Switching Characteristics
Symbol
Rref
Conditions
Min
2.5
Typ
5
Max
7.5
±25
Unit
s
kΩ
v
(test conditions Ta=+25C)
Parameter
Strobe Width
Data Setup Time
Data Hold Time
Symbol
t
SW
t
DS
t
DH
Conditions
HBE and LBE Inputs
Bit 1 to Bit 16
Bit 1 to Bit 16
Min
80
80
40
Typ
60
70
20
Max
Unit
s
ns
ns
ns
NOTES:
1. Integral Nonlinearity is measured as the arithmetic
mean value of magnitudes of the greatest positive
deviation and the greatest negative deviation from the
theoretical value of any given input combination.
2. Differential Nonlinearity DNL is the deviation of an
output step from the theoretical value of 1 LSB for any
two adjacent digital input codes.
3.Guaranteed by design but not production tested.
4.Logic inputs are MOS gates. Iin typical is less than 1
nA at 25C.
4
DA9316.003
March 23, 2005
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for design guidance only and are subject to sample testing only. VDD=+15V,
VREF=10V, IO1=IO2=DGND=0V except where stated. Output Amp is HOS-050.
(test conditions Ta=+25C)
Parameter
Propagation Delay
Symbol
t
PD
Conditions
IO1 load R=100Ω, Cext=13pF
All Data Inputs 0V to VDD or
VDD to 0V
From 50% digital input change
to 90% of final analog output.
TIMESettling
to +0.01% FSR (strobed).
0111111111111111 to
1000000000000000 or
1000000000000000 to
0111111111111111
All Data Inputs 0V to VDD or
VDD to 0V
Digital inputs VIH
Digital inputs VIH
Digital inputs VIL
Digital inputs VIL
Min
Typ
300
Max
Units
ns
CURRENT SETTLING
Major Code Transition
ts
1.5
µS
Full Scale Transition
OUTPUT CAPACITANCE
CIO1 (Pin 16)170
CIO2 (Pin 15)
CIO1 (Pin 16)
CIO2 (Pin 15)
Digital to Analog Glitch
Energy
Multiplying Feedthrough
Error at IO1
Power Supply Rejection
Ratio
Co
3.0
µs
170
30
80
100
250
pF
pF
pF
pF
nVs
Q
VREF =0V
DAC register alternately loaded
with all 0s and all 1s
VREF=20Vpp; f=10kHz sine wave
VREF=20Vpp, f=1kHz sine wave
VDD = 14 to 16V
FT
PSRR
3.0
0.3
±0.0001
±0.002
mVpp
mVpp
%/%
TIMING DIAGRAM
DATA
t1
t1
LAT CH
O UTPU T
t2
t2
t3
t1 = Data Setup Tim e (8 0ns)
t2 = Stro be W idth (80ns)
t3 = Se ttling Tim e (2us typical)
5
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