HM 9270C/D
DTMF RECEIVER
General Description
The HM 9270C/D is a complete DTMF receiver integrating both the bandsplit filter and digital decoder
functions. The filter section uses switched capacitor techniques for high- and low-group filters and dial-tone
rejection. Digital counting techniques are employed in the decoder to detect and decode all 16 DTMF tone-
pairs into a 4-bit code. External component count is minimized by on-chip provision of a differential input
amplifier, clock-oscillator and latched 3-state bus interface.
Features
•
•
•
•
•
•
•
•
Complete receiver in an 18-pin package.
Excellent performance.
CMOS, single 5 volt operation.
Minimum board area.
Central office quality.
Low power consumption.
Power-Down mode (HM9270D only).
Inhibit-mode (HM9270D only).
Pin Configurations
HM9270C
IN+
IN
GS
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
V
DD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE
IN+
IN
GS
HM9270D
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
V
DD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE
V
REF
IC*
IC*
OSC1
OSC2
V
SS
V
REF
INH
PWDN
OSC1
OSC2
V
SS
* Connect to V
SS
- 1 -
HM 9270C/D
DTMF RECEIVER
Block Diagram (Figure 1)
INH
HIGH
GROUP
FILTER
IN+
IN
DIGITAL
ZERO
CROSSING
DETECTORS DETECTION
CODE
CONVERTER
AND
Q1
Q2
Q3
Q4
+
-
DIAL
TONE
FILTER
LOW
GROUP
FILTER
ALGORITHM
LATCH
GS
CHIP
CHIP CHIP
CHIP
POWER BIAS REF
CLOCKS
OSC2
BIAS
CIRCUIT
+
-
STEERING
LOGIC
OSC1
V
DD
V
SS
PWDN
V
REF
St/
GT
ESt
StD
TOE
Pin Description
Pin
1
2
3
Sym.
IN+
IN-
GS
Function
Non-Inverting input
Connections to the front-end differential amplifier.
Invering Input
Gain select. Gives access to output of front-end differential amplifier for connection of
feedback resistor.
Reference voltage output,nominally V
DD
/2. May be used to bias the inputs at midrail (see
application diagram).
Inhibit (input) logic high inhibit the detection of 1633Hz internal built-in pull down resistor.
(HM9270D only).
Power down (input). Active high power down the device and inhibit the oscillator internal
built-in pull down resistor. (HM9270D only).
Clock Input
Output
Clock
3.579545 MHz crystal connected between these pins completes
internal oscillator.
4
V
REF
INH
5
6
PWDN
7
8
9
10
OSC1
OSC2
V
SS
TOE
Negative power supply, normally connected to 0V.
3-state data output enable (input). Logic high enables the outputs Q1-Q4. Internal pull-up.
- 2 -
HM 9270C/D
DTMF RECEIVER
Pin
11
12
13
14
15
Sym.
Q1
Q2
Q3
Q4
StD
Function
3-state data outputs. When enabled by TOE, provide the code corresponding to the last valid
tone-pair received (see code table).
Delayed steering output. Presents a logic high when a received tone-pair has been registered
and the output latch updated; returns to logic low when the voltage on St/GT falls below
V
TSt
.
Early steering output. Presents a logic high immediately when the digital algorithm detects a
recognizable tone-pair (signal condition). Any momentary loss of signal condition will cause
ESt to return to a logic low.
Steering input/guard time output (bi-directional). A voltage greater than V
TSt
detected at St
causes the device to register the detected tone-pair and update the output latch. A voltage
less than V
TSt
frees the device to accept a new tone-pair. The GT output acts to reset the
external steering time-constant; its state is a function of ESt and the voltage on St (see truth
table).
Positive power supply, +5Volts.
16
ESt
17
St/GT
18
V
DD
Absolute Maximum Ratings
(Notes 1, 2 and 3)
Parameters
Min.
Max.
Units
Power Supply Voltage, V
DD
- V
SS
6
V
Voltage on any pin
V
SS
- 0.3
V
DD
+ 0.3
V
Current at any pin
10
mA
o
Operating temperature
-40
+85
C
o
Storage temperature
-65
+150
C
Package power dissipation
500
mW
Note
1. Absolute maximum ratings are those values beyond which damage to the device may
occur.
2. Unless otherwise specified, all voltages are referenced to ground.
3. Power dissipation temperature derating: -12
mV
/
oC
from 65
o
C to 85
o
C
DC Electrical Characteristics
Parameter Description
SUPPLY:
V
DD
I
cc
P
o
I
S
INPUTS:
V
IL
V
IH
I
IH
/I
IL
I
so
R
IN
V
TSt
Operating Supply Voltage
Operating Supply Current
Power Consumption
Standby Current
Test Conditions
Min. Typ. Max. Units
4.75
5.25
7
35
100
V
mA
mW
µA
f=3.579MHz; V
DD
=5V
PWDN pin = V
DD
-
3.0
15
-
Low Level Input Voltage
High Level Input Voltage
Input Leakage Current
Pull Up (Source) Current
Input
Signal
Impedance Inputs 1,2
Steering Threshold Voltage
1.5
3.5
V
IN
=V
ss
or V
DD
TOE (Pin 10)=OV
@ 1kHz
0.1
7.5
10
2.35
- 3 -
15
V
V
uA
uA
MΩ
V
HM 9270C/D
DTMF RECEIVER
Parameter
OUTPUTS:
V
OL
V
OH
I
OL
I
OH
V
REF
R
OR
Description
Test Conditions
No Load
No Load
V
OUT
=0.4V
V
OUT
=4.6V
No Load
Min.
Typ.
0.03
4.97
2.5
0.8
Max.
Units
V
V
mA
mA
V
KΩ
Low Level Output Voltage
High Level Output Voltage
Output Low (Sink) Current
Output High (Source) Current
Output Voltage
V
REF
Output Resistance
1.0
0.4
2.4
2.7
10
Operating Characteristics
Gain Setting Amplifier
Parameter
I
IN
R
IN
V
OS
PSRR
CMRR
A
VOL
f
C
V
O
C
L
R
L
V
CM
Description
Input Leakage Current
Input Resistance
Input Offset Voltage
Power Supply Rejection
Common Mode Rejection
DC Open Loop Voltage Gain
Open Loop Unity Gain Bandwidth
Output Voltage Swing
Tolerable capacitive load(GS)
Tolerable resistive load(GS)
Common Mode Range
Test Conditions
V
SS
< V
IN
< V
DD
Min.
Typ. Max.
±100
10
±25
60
60
65
1.5
4.5
100
50
3.0
Units
nA
MΩ
mV
dB
dB
dB
MHz
V
PP
pF
KΩ
V
PP
1kHz
-3.0V <V
IN
< 3.0V
R
L
³100KΩ to V
SS
No Load
Notes
: 1.All voltages referenced to V
DD
unless otherwise noted.
2.V
DD
= 5.0V, V
SS
= 0V, T
A
= 25
o
C .
AC Characteristics
All voltages referenced to V
SS
unless otherwise noted. V
DD
=5.0V, V
SS
=0V, T
A
= 25
O
C, F
CLK
=3.579545 MNz, using
test circuit of figure 2.
Parameter
Description
Min.
Typ.
Max. Units
Notes
SIGNAL COITIONS:
Valid Input Signal level (each
tone signal):MIN
MAX
+1
883
10
10
-40
7.75
dBm
mV
RMS
dBm
mV
RMS
dB
dB
Nom.
Nom.
dB
dB
1,2,3,5,6,9,11
1,2,3,5,6,9,11
1,2,3,5,6,9,11
2,3,6,9,11
Twist Accept Limit: Positive
Negative
Freq. Deviation Accept Limit
Freq. Deviation Reject Limit
Third Tone Tolerance
Noise Tolerance
Dial Tone Tolerance
±1.5%±2 Hz
±3.5%
-16
-12
+18
2,3,5,9,11
2,3,5,11
2,3,4,5,9,10,11
2,3,4,5,7,9,10,11
2,3,4,5,8,9,10,11
- 4 -
HM 9270C/D
DTMF RECEIVER
Parameter
TIMING:
t
DP
t
DA
t
REC
t
REC
t
ID
t
DO
OUTPUTS:
t
PQ
t
PSED
t
QSED
t
PTE
t
PTD
CLOCK:
f
CLK
C
LO
Description
Tone Present Detection Time
Tone Absent Detection Time
Tone Duration Accept
Tone Duration Reject
Interdigit Pause Accept
Interdigit Pause Reject
Min. Typ. Max.
5
0.5
20
40
ms
14
4
16
8.5
40
Units
ms
ms
ms
ms
ms
Notes
Refer to Fig. 4
(User Adjustable)
Refer to "Guard Time
20
Adjustment"
Propagation Delay (St to Q)
Propagation Delay (St to StD)
Output Data Set Up (Q to Std)
Propagation
ENABLE
Delay (TOE to Q) DISABLE
8
12
4.5
50
300
11
60
µs
µs
µs
ns
ns
TOE= V
DD
R
L
=10kΩ
C
L
=50pf
Crystal/Clock Frequency
Clock Output Capacitive
(OSC2)
Load
3.5759 3.5795
3.581 MHz
30 pf
Notes:
1.dBm = decibels above or below a reference power of 1mW into a 600 Ohm load.
2.Digit sequences consists of all 16 DTMF tones.
3.Tone duration = 40mS Tone pause = 40mS.
4.Nominal DTMF frequencies are used.
5.Both tones in the composite signal have an equal amplitude.
6.Tone pair is deviated by ±1.5% ±2Hz.
7.Bandwidth limited (3kHz) Gaussian Noise.
8.The precise dial tone frequencies are (350Hz and 440Hz) ±2%.
9.For an error rate of less than 1 in 10,000.
10.Referenced to the lowest level frequency component in DTMF signal.
11.Added A 0.1µf capacitor between V
DD
and V
SS
.
Function Description
HM9270C
5V
0.1µf
100
NF
100 KΩ
100 KΩ
IN+
IN
GS
V
REF
IC
IC
3.58
MHz
OSC1
OSC2
V
SS
V
DD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE
100
NF
300 KΩ
FIGURE 2. SINGLE ENDED INPUT CONFIGURATION
- 5 -
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