Preliminary
PLL102-109
Programmable DDR Zero Delay Clock Driver
FEATURES
•
•
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•
PLL clock distribution optimized for Double Data
Rate SDRAM application up to 266Mhz.
Distributes one clock Input to one bank of six
differential outputs.
Track spread spectrum clocking for EMI reduction.
Programmable delay between CLK_INT and CLK[T/C]
from –0.8ns to +3.1ns by programming CLKINT and
FBOUT skew channel, or from –1.1ns to +3.5ns if
additional DDR skew channels are enabled.
Two independent programmable DDR skew chan-
nels from –0.3ns to +0.4ns with step size
±100ps.
Support 2-wire I
2
C serial bus interface.
2.5V Operating Voltage.
Available in 28-Pin 209mil SSOP.
PIN CONFIGURATION
CLKCO
CLKT0
VDD
CLKT1
CLKC1
GND
SCLK
CLK_INT
N/C
AVDD
AGND
VDD
CLKT2
CLKC2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
CLKC5
CLKT5
CLKC4
CLKT4
VDD
SDATA
N/C
FB_INT
FB_OUTT
ADDR_SEL
CLKT3
CLKC3
GND
PLL102-109
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DESCRIPTIONS
The PLL102-109 is a zero delay buffer that distributes
a single-ended clock input to six pairs of differential
clock outputs and one feedback clock output. Output
signal duty cycles are adjusted to 50%, independent of
the duty cycle at CLK_INT. The PLL can be bypassed
for test purposes by strapping AV
DD
to ground.
BLOCK DIAGRAM
Programmable
Skew Channel
-600~+800ps
±200ps step
AV
DD
Programmable
Delay Channel
CLK_INT
(0~2.5ns)
+170ps step
PLL
FB_INT
AV
DD
-300~+400ps
±100ps step
Control
Logic
-300~+400ps
±100ps step
FB_OUTT
CLKT0
CLKC0
CLKT1
CLKC1
CLKT5
CLKC5
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 02/26/03 Page 1
Preliminary
PLL102-109
Programmable DDR Zero Delay Clock Driver
PIN DESCRIPTIONS
Name
VDD
GND
AVDD
AGND
CLKT(0:5)
CLKC(0:5)
CLK_INT
ADDR_SEL
N/C
FB_OUTT
FB_INT
SDATA
SCLK
Number
3,12,23
6,15,28
10
11
2,4,13,17,24,26
1,5,14,16,25,27
8
18
9,21
19
20
22
7
Type
PWR
PWR
PWR
PWR
OUT
OUT
IN
IN
-
OUT
IN
I/O
IN
2.5V power supply.
Ground
Analog power supply (2.5V).
Analog ground.
Description
“True” clocks of differential pair outputs.
“Complementary” clocks of differential pair outputs.
Single-ended 3.3V tolerant input.
If ADDR_SEL=0(default) Write condition (0xD4) or a read condition (0xD5)
If ADDR_SEL=1, Write condition (0xD6) or a read condition (0xD7)
Not connected.
“True” feedback output. Dedicated for external feedback. It switches at the
same frequency as the CLK_INT.
“True” feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error.
Serial data input for serial interface port.
Functionality
INPUTS
AVDD
2.5V (Nom)
2.5V (Nom)
GND
GND
CLK_INT
L
H
L
H
CLK_INC
H
L
H
L
CLKT
L
H
L
H
OUTPUTS
CLKC
H
L
H
L
FB_OUTT
L
H
L
H
PLL State
On
On
Bypass/Off
Bypass/Off
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 02/26/03 Page 2
Preliminary
PLL102-109
Programmable DDR Zero Delay Clock Driver
I2C BUS CONFIGURATION SETTING
Address Assignment
Slave Re-
ceiver/Transmitter
Data Transfer Rate
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
_
Provides both slave write and read back functionality
Standard mode at 100kbits/s
This serial protocol is designed to allow both blocks write and read from the controller. The
bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred
must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will termi-
nate the transfer. The write or read block both begins with the master sending a slave address
and a write condition (0xD4) or a read condition (0xD5).
Following the acknowledge of this address byte, in
Write Mode:
the
Command Byte
and
Byte
Count Byte must be sent by the master
but ignored by the slave, in
Read Mode:
the
Byte
Count Byte
will be
read by the master
then all other
Data Byte. Byte Count Byte
default at
power-up is = (0x09).
Data Protocol
I2C CONTROL REGISTERS
1. BYTES 0 TO 4
are reserved power up default =1.
2. BYTE 5: Outputs Register
(1=Enable, 0=Disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
-
-
26,27
24,25
16,17
13,14
4,5
1,2
Default
-
-
1
1
1
1
1
1
Description
Reserved
Reserved
CLKT5, CLKC5 (1= active, 0=inactive)
CLKT4, CLKC4 (1= active, 0=inactive)
CLKT3, CLKC3 (1= active, 0=inactive)
CLKT2, CLKC2 (1= active, 0=inactive)
CLKT1, CLKC1 (1= active, 0=inactive)
CLKT0, CLKC0 (1= active, 0=inactive)
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 02/26/03 Page 3
Preliminary
PLL102-109
Programmable DDR Zero Delay Clock Driver
TABLE 1: Output Signals SKEW Programming Summary:
Bit<2:0>
111
110
101
100
011
010
001
000
DDR Skew Setting (± 100ps/step)
±
+400ps
+300ps
+200ps
+100ps
Default
-100ps
-200ps
-300ps
Setting applies to the following
outputs:
1. DDRA: CLK0, CLK1, CLK5
2. DDRB: CLK2, CLK3, CLK4.
FBOUT Skew Setting (± 200ps/step)
±
+800ps
+600ps
+400ps
+200ps
Default
-200ps
-400ps
-600ps
Setting applies to the following out-
puts:
1. FB_OUTT
3. BYTE 6: SKEW Register
(1=Enable, 0=Disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Skew
DDRA
-
Name
-
-
Bit <2>
Bit <1>
Bit <0>
-
-
-
Default
-
-
0
1
1
-
-
-
Reserved
Reserved
Description
These three bits will adjust timing of DDRA signals (CLK0, CLK1,
CLK5) either positive or negative delay up to +400ps or –300ps
with
±100ps
per step. (see Table 1)
Reserved
Reserved
Reserved
-
-
4. BYTE 7: SKEW Register
(1=Enable, 0=Disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
DDR-SKEWEN
FBOUT-SKEWEN
Skew
DDRC
-
Bit <2>
Bit <1>
Bit <0>
-
-
-
Default
1
1
0
1
1
-
-
-
1= disable, 0= enable
1= disable, 0= enable
Description
These three bits will adjust timing of DDRC signals (CLK2, CLK3,
CLK4) either positive or negative delay up to +400ps or –300ps
with
±100ps
per step. (see Table 1)
Reserved
Reserved
Reserved
Rev 02/26/03 Page 4
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47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Preliminary
PLL102-109
Programmable DDR Zero Delay Clock Driver
5. BYTE 8: Outputs Register
(1=Enable, 0=Disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Delay
CLKINT
Skew
FBOUT
Name
-
Bit <2>
Bit <1>
Bit <0>
Bit <3>
Bit <2>
Bit <1>
Bit <0>
Default
1
0
1
1
0
0
0
0
Reserved
Description
These three bits will adjust timing of FBOUTT signal either positive
or negative delay up to +800ps or –600ps with
±200ps
per step.
(see Table 1)
These four bits will program the propagation delay from CLK_INT
to the input of PLL within the range between 0ps and 2.5ns with
170ps step size. (see Table 2)
TABLE 2: CLK_INT Delay Programming Summary:
Bit<3:0>
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
CLK_INT to CLK Delay
+2,550 ps
+2,380 ps
+2,210 ps
+2,040 ps
+1,870 ps
+1,700 ps
+1,530 ps
+1,360 ps
+1,190 ps
+1,020 ps
+850 ps
+680 ps
+510 ps
+340 ps
+170 ps
Default
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 02/26/03 Page 5
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