Internal phase locked loop will allow spread spec-
trum modulation on reference clock to pass to the
outputs (up to 100kHz SST modulation).
Zero input - output delay.
Less than 700 ps device - device skew.
Less than 250 ps skew between outputs.
Less than 200 ps cycle - cycle jitter.
Output Enable function tri-state outputs.
3.3V operation.
Available in 8-Pin 150mil SOIC.
Remark
If REF clock is stopped for more than 10us after it has already been
provided to the chip, and after power-up, the output clocks will
disappear. In that instance, a full power-up reset is required in order
to reactivate the output clocks.
PIN CONFIGURATION
REF
CLK2
CLK1
GND
1
2
3
4
8
7
6
5
CLKOUT
CLK4
VDD
CLK3
PLL102-04
DESCRIPTION
The PLL102-04 is a high performance, low skew, low
jitter zero delay buffer designed to distribute high
speed clocks and is available in 8-pin SOIC package. It
has four outputs that are synchronized with the input.
The synchronization is established via CLKOUT feed
back to the input of the PLL. Since the skew between
the input and output is less than
±350
ps, the device
acts as a zero delay buffer.
BLOCK DIAGRAM
REF
PLL
CLKOUT
CLK1
CLK2
CLK3
CLK4
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/22/05 Page 1
PLL102-04
Low Skew Output Buffer
PIN DESCRIPTIONS
Name
REF
1
CLK2
2
CLK1
2
GND
CLK3
2
VDD
CLK4
2
CLKOUT
2
Number
1
2
3
4
5
6
7
8
Type
I
O
O
P
O
P
O
O
Description
Input reference frequency. Spread spectrum modulation on this signal will be
passed to the output (up to 100kHz SST modulation).
Buffered clock output.
Buffered clock output.
Ground.
Buffered clock output.
3.3V Power Supply.
Buffered clock output.
Buffered clock output. Internal feed back on this pin.
Notes:
1: Weak pull-down. 2: Weak pull-down on all outputs.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con-
ditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Electrical Characteristics
PARAMETERS
Supply Voltage
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Power Down Supply Current
Supply Current
SYMBOL
V
DD
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
I
DD
CONDITIONS
MIN.
2.97
2.0
TYP.
MAX.
3.63
0.8
UNITS
V
V
V
µA
µA
V
V
µA
mA
V
IN
= 0V
V
IN
= V
DD
I
OL
= 50mA
I
OH
= 50mA
REF = 0MHz
Unloaded outputs at 133MHz,
SEL inputs at V
DD
or GND
2.4
19
0.10
0.25
2.9
0.3
35
50.0
100.0
0.4
50.0
45
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/22/05 Page 2
PLL102-04
Low Skew Output Buffer
3. Switching Characteristics
PARAMETERS
Output Frequency
Duty Cycle ( t2
÷
t1 )
Duty Cycle ( t2
÷
t1 )
Rise Time
Fall Time
Output to Output Skew
Delay, REF Rising Edge to
CLKOUT Rising Edge
Device to Device Skew
Cycle to Cycle Jitter
PLL Lock Time
Jitter; Absolute Jitter
Jitter; 1-sima
SYMBOL
t1
Dt1
Dt2
T
r
T
f
T
skew
T
delay
T
dsk-dsk
T
cyc-cyc
T
lock
T
jabs
T
j1-s
DESCRIPTION
Measured at 1.4V,
C
L
=30pF, F
out
= 66.67MHz
Measured at 1.4V
Measured between 0.8V
and 2.0V, C
L
=30pF
Measured between 2.0V
and 0.8V, C
L
=30pF
All outputs equally loaded,
C
L
=20pF
Measured at 1.4V
Measured at V
DD
/2 on the
CLKOUT pins of devices
Measured at 66.67MHz,
loaded outputs
Stable power supply, valid
clock presented on REF pin
At 10,000 cycles, C
L
=30pF
At 10,000 cycles, C
L
=30pF
MIN.
50
40.0
45.0
TYP.
50.0
50.0
1.2
1.2
MAX.
120
60.0
55.0
1.5
1.5
250
UNITS
MHz
%
%
ns
ns
ps
ps
ps
ps
ms
ps
ps
0
0
±350
700
150
1.0
70
10
100
20
SWITCHING WAVEFORMS
Duty Cycle Timing
t1
t2
1.4V
1.4V
1.4V
Output - Output Skew
Output
1.4V
1.4V
Output
T
SKEW
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/22/05 Page 3
PLL102-04
Low Skew Output Buffer
SWITCHING WAVE FORMS
All Outputs Rise/Fall Time
2.0V
2.0V
0.8V
t
r
t
f
3.3V
0V
Output
0.8V
Input to Output Propagation Delay
Input
V
DD
/2
Output
V
DD
/2
T
delay
Device to Device Skew
Device1 CLKOUT
V
DD
/2
Device2 CLKOUT
V
DD
/2
T
dsk - dsk
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/22/05 Page 4
PLL102-04
Low Skew Output Buffer
Output-Output Skew
The skew between CLKOUT and the CLK(1-4) outputs is not dynamically adjusted by the
PLL. Since CLKOUT is one of the inputs to the PLL, zero phase difference is maintained
from REF to CLKOUT. If all outputs are equally loaded, zero phase difference will
maintained from REF to all outputs.
If applications requiring zero output-output skew, all the outputs must equally loaded.
If the CLK(1-4) outputs are less loaded than CLKOUT, CLK(1-4) outputs will lead it; if the
CLK(0-4) is more loaded than CLKOUT, CLK(1-4) will lag the CLKOUT.
Since the CLKOUT and the CLK(1-4) outputs are identical, they all start at the same time,
but difference loads cause them to have different rise times and different times crossing
the measurement thresholds.
REF
CLKOUT
CLK(1-4)
Zero Delay
REF input and all outputs loaded equally
REF
CLKOUT
CLK(1-4)
Advanced
REF input and CLK(1-4) outputs loaded equally,
with CLK(1-4) less loaded than CLKOUT.
REF
CLKOUT
CLK(1-4)
Delayed
REF input and CLK(1-4) outputs loaded equally, with
CLK(1-4) more loaded than CLKOUT.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
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