74HC73-Q100
Rev. 1 — 4 December 2020
Dual JK flip-flop with reset; negative-edge trigger
Product data sheet
1. General description
The 74HC73-Q100 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP)
and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be
stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (nR)
is asynchronous, when LOW it overrides the clock and data inputs, forcing the nQ output LOW
and the nQ output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant
to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current
limiting resistors to interface inputs to voltages in excess of V
CC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
•
•
•
•
•
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
•
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
CMOS low-power dissipation
Wide supply voltage range from 2.0 to 6.0 V
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards
•
JESD8C (2.7 V to 3.6 V)
•
JESD7A (2.0 V to 6.0 V)
ESD protection:
•
HBM JESD22-A114F exceeds 2000 V
•
MM JESD22-A115-A exceeds 200 V
•
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74HC73D-Q100
-40 °C to +125 °C
Name
SO14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
Version
SOT108-1
Nexperia
74HC73-Q100
Dual JK flip-flop with reset; negative-edge trigger
4. Functional diagram
14 1J
1 1CP
3 1K
J
FF1
CP
K
R
Q
1Q 12
Q
1Q 13
2 1R
14
1
7 2J
5 2CP
10 2K
J
FF2
CP
K
R
6 2R
001aab981
1J
C1
1K
R
12
13
Q
2Q 9
14
7
1J
2J
J
CP
K
R
1R 2R
2 6
FF
1Q 12
Q
2Q 9
3
2
1 1CP
5 2CP
Q
2Q 8
3
10
1K
2K
Q
1Q 13
2Q 8
7
5
10
6
1J
C1
1K
R
001aab980
9
8
001aab979
Fig. 1.
Functional diagram
Fig. 2.
C
Logic symbol
C
C
Fig. 3.
C
IEC logic symbol
K
Q
J
C
R
C
C
001aab982
C
C
C
Q
CP
Fig. 4.
Logic diagram (one flip-flop)
74HC73_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 1 — 4 December 2020
2 / 12
Nexperia
74HC73-Q100
Dual JK flip-flop with reset; negative-edge trigger
5. Pinning information
5.1. Pinning
74HC73
1CP
1R
1K
V
CC
2CP
2R
2J
1
2
3
4
5
6
7
001aab978
14 1J
13 1Q
12 1Q
11 GND
10 2K
9
8
2Q
2Q
Fig. 5.
Pin configuration SOT108-1 (SO14)
5.2. Pin description
Table 2. Pin description
Symbol
Pin
1CP, 2CP
1R, 2R
1K, 2K
V
CC
GND
1Q, 2Q
1Q, 2Q
1J, 2J
1, 5
2, 6
3, 10
4
11
12, 9
13, 8
14, 7
Description
clock input (HIGH-to-LOW edge-triggered); also referred to as nCP
asynchronous reset input (active LOW); also referred to as nR
synchronous K input; also referred to as nK
positive supply voltage
ground (0 V)
true output; also referred to as nQ
complement output; also referred to as nQ
synchronous J input; also referred to as nJ
6. Functional description
Table 3. Function table
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition;
L = LOW voltage level; I = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition;
q = state of referenced output one set-up time prior to the HIGH-to-LOW clock transition;
X = don’t care; ↓ = HIGH-to-LOW clock transition.
Input
nR
L
H
H
H
H
nCP
X
↓
↓
↓
↓
nJ
X
h
l
h
l
nK
X
h
h
l
l
Output
nQ
L
q
L
H
q
nQ
H
q
H
L
q
asynchronous reset
toggle
load 0 (reset)
load 1 (set)
hold (no change)
Operating mode
74HC73_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 1 — 4 December 2020
3 / 12
Nexperia
74HC73-Q100
Dual JK flip-flop with reset; negative-edge trigger
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Conditions
V
I
< -0.5 V or V
I
> V
CC
+ 0.5 V
V
O
< -0.5 V or V
O
> V
CC
+ 0.5 V
V
O
= -0.5 V to V
CC
+ 0.5 V
[1]
[1]
Min
-0.5
-
-
-
-
-50
-65
Max
+7.0
±20
±20
±25
50
-
+150
500
Unit
V
mA
mA
mA
mA
mA
°C
mW
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
T
amb
= -40 °C to +125 °C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SOT108-1 (SO14) package: P
tot
derates linearly with 10.1 mW/K above 100 °C.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter
V
CC
V
I
V
O
T
amb
Δt/ΔV
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
Min
2.0
0
0
-40
-
-
-
Typ
5.0
-
-
-
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
Unit
V
V
V
°C
ns/V
ns/V
ns/V
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
1.5
3.15
4.2
-
-
-
25 °C
Typ
1.2
2.4
3.2
0.8
2.1
2.8
Max
-
-
-
0.5
1.35
1.8
-40 °C to +85 °C
Min
1.5
3.15
4.2
-
-
-
Max
-
-
-
0.5
1.35
1.8
-40 °C to
+125 °C
Min
1.5
3.15
4.2
-
-
-
Max
-
-
-
0.5
1.35
1.8
V
V
V
V
V
V
Unit
74HC73_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 1 — 4 December 2020
4 / 12
Nexperia
74HC73-Q100
Dual JK flip-flop with reset; negative-edge trigger
Conditions
Min
25 °C
Typ
2.0
4.5
6.0
4.32
5.81
0
0
0
0.15
0.16
-
-
3.5
Max
-
-
-
-
-
0.1
0.1
0.1
0.26
0.26
±0.1
4.0
-
-40 °C to +85 °C
Min
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
-
-
-
Max
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
±1.0
40.0
-
-40 °C to
+125 °C
Min
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
-
-
-
Max
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
±1.0
80.0
-
V
V
V
V
V
V
V
V
V
V
μA
μA
pF
Unit
Symbol Parameter
V
OH
V
I
= V
IH
or V
IL
HIGH-level
output voltage
I
O
= -20 μA; V
CC
= 2.0 V
I
O
= -20 μA; V
CC
= 4.5 V
I
O
= -20 μA; V
CC
= 6.0 V
I
O
= -4 mA; V
CC
= 4.5 V
I
O
= -5.2 mA; V
CC
= 6.0 V
1.9
4.4
5.9
3.98
5.48
-
-
-
-
-
-
-
-
V
OL
V
I
= V
IH
or V
IL
LOW-level
output voltage
I
O
= 20 μA; V
CC
= 2.0 V
I
O
= 20 μA; V
CC
= 4.5 V
I
O
= 20 μA; V
CC
= 6.0 V
I
O
= 4 mA; V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
I
I
I
CC
C
I
input leakage
current
V
I
= V
CC
or GND; V
CC
= 6.0 V
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
input
capacitance
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit, see
Fig. 8
Symbol Parameter
Conditions
Min
t
pd
propagation
delay
nCP to nQ; see
Fig. 6
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
CC
= 5.0 V; C
L
= 15 pF
nCP to nQ; see
Fig. 6
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
CC
= 5.0 V; C
L
= 15 pF
nR to nQ, nQ; see
Fig. 7
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
CC
= 5.0 V; C
L
= 15 pF
-
-
-
-
50
18
14
15
145
29
25
-
-
-
-
180
36
31
-
-
-
-
-
220
44
38
-
ns
ns
ns
ns
-
-
-
-
52
19
15
16
160
32
27
-
-
-
-
200
40
34
-
-
-
240
48
41
ns
ns
ns
ns
[1]
-
-
-
-
52
19
15
16
160
32
27
-
-
-
-
-
200
40
34
-
-
-
-
-
240
48
41
-
ns
ns
ns
ns
25 °C
Typ
Max
-40 °C to +85 °C
Min
Max
-40 °C to
+125 °C
Min
Max
Unit
74HC73_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 1 — 4 December 2020
5 / 12
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