®
PX3511A, PX3511B
Data Sheet
February 26, 2007
FN6462.0
Advanced Synchronous Rectified Buck
MOSFET Drivers with Protection Features
The PX3511A and PX3511B are high frequency MOSFET
drivers specifically designed to drive upper and lower power
N-Channel MOSFETs in a synchronous rectified buck
converter topology. These drivers combined with the
ISL6595 Digital Multi-Phase Buck PWM controller and
N-Channel MOSFETs form a complete core-voltage
regulator solution for advanced microprocessors.
The PX3511A drives the upper gate to 12V, while the lower
gate can be independently driven over a range from 5V to
12V. The PX3511B drives both upper and lower gates over a
range of 5V to 12V. This drive-voltage provides the flexibility
necessary to optimize applications involving trade-offs
between gate charge and conduction losses.
An adaptive zero shoot-through protection is integrated to
prevent both the upper and lower MOSFETs from conducting
simultaneously and to minimize the dead time. These
products add an overvoltage protection feature operational
before VCC exceeds its turn-on threshold, at which the
PHASE node is connected to the gate of the low side
MOSFET (LGATE). The output voltage of the converter is
then limited by the threshold of the low side MOSFET, which
provides some protection to the microprocessor if the upper
MOSFET(s) is shorted during initial start-up.
These drivers also feature a three-state PWM input which,
working together with Intersil’s multi-phase PWM controllers,
prevents a negative transient on the output voltage when the
output is shut down. This feature eliminates the Schottky
diode that is used in some systems for protecting the load
from reversed output voltage events.
Features
• Dual MOSFET Drives for Synchronous Rectified Bridge
• Adjustable Gate Voltage (5V to 12V) for Optimal Efficiency
• 36V Internal Bootstrap Schottky Diode
• Bootstrap Capacitor Overcharging Prevention
• Supports High Switching Frequency (up to 2MHz)
- 3A Sinking Current Capability
- Fast Rise/Fall Times and Low Propagation Delays
• Three-State PWM Input for Output Stage Shutdown
• Three-State PWM Input Hysteresis for Applications With
Power Sequencing Requirement
• Pre-POR Overvoltage Protection
• VCC Undervoltage Protection
• Expandable Bottom Copper Pad for Enhanced Heat
Sinking
• Dual Flat No-Lead (DFN) Package
- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Core Regulators for Intel® and AMD® Microprocessors
• High Current DC/DC Converters
• High Frequency and High Efficiency VRM and VRD
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief TB417 for Power Train Design, Layout
Guidelines, and Feedback Compensation Design
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
PX3511A, PX3511B
Ordering Information
PART NUMBER
PX3511ADAG (Note)
PX3511ADAG-R3 (Note)
PX3511ADDG
PX3511ADDG-RA
PX3511BDAG (Note)
PX3511BDAG-R3 (Note)
PX3511BDDG
PX3511BDDG-RA
PART MARKING
PX3511 ADAG
PX3511 ADAG
11AD
11AD
PX351 BDAG
PX3511 BDAG
11BD
11BD
TEMP. RANGE (°C)
0 to +85
0 to +85
0 to +85
0 to +85
0 to +85
0 to +85
0 to +85
0 to +85
PACKAGE
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free) Tape and Reel
10 Ld 3x3 DFN
10 Ld 3x3 DFN Tape and Reel
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free) Tape and Reel
10 Ld 3x3 DFN
10 Ld 3x3 DFN Tape and Reel
PKG. DWG. #
M8.15
M8.15
L10.3x3
L10.3x3
M8.15
M8.15
L10.3x3
L10.3x3
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinouts
PX3511ACB, PX3511BCB
(8 LD SOIC)
TOP VIEW
UGATE
BOOT
PWM
GND
1
2
3
4
8
7
6
5
PHASE
PVCC
VCC
LGATE
PX3511ACR, PX3511BCR
(10 LD 3x3 DFN)
TOP VIEW
CRD L
UGATE
1
2
3
4
5
10
9
8
7
6
BAT
PHASE
BOOT
USB
N/C
PPR
PW M
C HG
NTC or
GND
OVP
or EN
PVCC
ICDL
GND
N/C
VCC
USBP
IUSB
LGATE
Block Diagram
PX3511A AND PX3511B
UVCC
VCC
+5V
10K
PWM
POR/
CONTROL
8K
LOGIC
LGATE
Pre-POR OVP
FEATURES
BOOT
UGATE
PHASE
(LVCC)
PVCC
UVCC = VCC FOR PX3511A
UVCC = PVCC FOR PX3511B
SHOOT-
THROUGH
PROTECTION
GND
PAD
FOR DFN -DEVICES, THE PAD ON THE BOTTOM SIDE OF
THE PACKAGE MUST BE SOLDERED TO THE CIRCUIT’S GROUND.
2
FN6462.0
February 26, 2007
Typical Application - 4 Channel Converter Using ISL6595 and PX3511A Gate Drivers
+12V
PX3511
+5V
1 UGATE
2 BOOT
3 PWM
4 GND
PHASE 8
PVCC 7
VCC 6
LGATE 5
3
+3.3V
VDD
V12_SEN
GND
PX3511
1 UGATE
2 BOOT
3 PWM
4 GND
PHASE 8
PVCC 7
VCC 6
ISL6595
VID4
VID3
VID2
VID1
FROM µP
VID0
VID5
LL0
LL1
OUTEN
OUT1
OUT2
ISEN1
OUT3
OUT4
ISEN2
OUT5
OUT6
ISEN3
OUT7
OUT8
PX3511A, PX3511B
LGATE 5
Vout
PX3511
1 UGATE
2 BOOT
3 PWM
4 GND
PHASE 8
PVCC 7
VCC 6
LGATE 5
RTN
TO µP
VCC_PWRGD
ISEN4
OUT9
RESET_N
OUT10
ISEN5
PX3511
1 UGATE
2 BOOT
3 PWM
4 GND
PHASE 8
PVCC 7
VCC 6
LGATE 5
FAULT
OUTPUTS
FAULT1
FAULT2
OUT11
OUT12
ISEN6
SDA
I2C I/F
BUS
SCL
SADDR
FN6462.0
February 26, 2007
TEMP_SEN
RTHERM
CAL_CUR_EN
CAL_CUR_SEN
VSENP
VSENN
PX3511A, PX3511B
Absolute Maximum Ratings
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V
BOOT Voltage (V
BOOT
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36V
Input Voltage (V
PWM
) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V
UGATE. . . . . . . . . . . . . . . . . . . V
PHASE
- 0.3V
DC
to V
BOOT
+ 0.3V
V
PHASE
- 3.5V (<100ns Pulse Width, 2µJ) to V
BOOT
+ 0.3V
LGATE . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V
DC
to V
PVCC
+ 0.3V
GND - 5V (<100ns Pulse Width, 2µJ) to V
PVCC
+ 0.3V
PHASE. . . . . . . . . . . . . . . GND - 0.3V
DC
to 15V
DC
(V
PVCC
= 12V)
GND - 8V (<400ns, 20µJ) to 30V (<200ns, VBOOT-GND<36V)
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD
Thermal Information
Thermal Resistance
θ
JA
(°C/W)
θ
JC
(°C/W)
SOIC Package (Note 1) . . . . . . . . . . . .
100
N/A
DFN Package (Notes 2, 3) . . . . . . . . . .
48
7
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
(SOIC - Lead Tips Only)
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . 0°C to +85°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . +125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V
±10%
Supply Voltage Range, PVCC . . . . . . . . . . . . . . . . 5V to 12V
±10%
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air.
2.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For
θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
VCC SUPPLY CURRENT
Bias Supply Current
Recommended Operating Conditions, Unless Otherwise Noted.
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
VCC
PX3511A, f
PWM
= 300kHz, V
VCC
= 12V
PX3511B, f
PWM
= 300kHz, V
VCC
= 12V
-
-
-
-
-
-
-
-
8
4.5
10.5
5
4
7.5
5
8.5
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
mA
I
VCC
PX3511A, f
PWM
= 1MHz, V
VCC
= 12V
PX3511B, f
PWM
= 1MHz, V
VCC
= 12V
Gate Drive Bias Current
I
PVCC
PX3511A, f
PWM
= 300kHz, V
PVCC
= 12V
PX3511B, f
PWM
= 300kHz, V
PVCC
= 12V
I
PVCC
(Note 4)
POWER-ON RESET AND ENABLE
VCC Rising Threshold
VCC Falling Threshold
PWM INPUT (See Timing Diagram on Page 6)
Input Current
I
PWM
PX3511A, f
PWM
= 1MHz, V
PVCC
= 12V
PX3511B, f
PWM
= 1MHz, V
PVCC
= 12V
9.35
7.35
9.8
7.6
10.0
8.0
V
V
V
PWM
= 3.3V
V
PWM
= 0V
-
-
-
-
1.23
-
-
-
505
-460
1.70
1.30
-
1.18
0.76
2.36
-
-
-
-
1.82
-
-
-
µA
µA
V
V
V
V
V
V
PWM Rising Threshold (Note 4)
PWM Falling Threshold (Note 4)
Typical Three-State Shutdown Window
Three-State Lower Gate Falling Threshold
Three-State Lower Gate Rising Threshold
Three-State Upper Gate Rising Threshold
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
4
FN6462.0
February 26, 2007
PX3511A, PX3511B
Electrical Specifications
PARAMETER
Three-State Upper Gate Falling Threshold
Shutdown Holdoff Time
UGATE Rise Time
LGATE Rise Time
UGATE Fall Time (Note 4)
LGATE Fall Time (Note 4)
UGATE Turn-On Propagation Delay (Note 4)
LGATE Turn-On Propagation Delay (Note 4)
UGATE Turn-Off Propagation Delay (Note 4)
LGATE Turn-Off Propagation Delay (Note 4)
LG/UG Three-State Propagation Delay (Note 4)
OUTPUT
Upper Drive Source Current (Note 4)
Upper Drive Source Impedance
Upper Drive Sink Current (Note 4)
Upper Drive Sink Impedance
Lower Drive Source Current (Note 4)
Lower Drive Source Impedance
Lower Drive Sink Current (Note 4)
Lower Drive Sink Impedance
NOTE:
4. Guaranteed by design. Not 100% tested in production.
I
U_SOURCE
V
PVCC
= 12V, 3nF Load
R
U_SOURCE
150mA Source Current
I
U_SINK
R
U_SINK
I
L_SOURCE
V
PVCC
= 12V, 3nF Load
150mA Sink Current
V
PVCC
= 12V, 3nF Load
-
1.4
-
0.9
-
0.85
-
0.60
1.25
2.0
2
1.65
2
1.3
3
0.94
-
3.0
-
3.0
-
2.2
-
1.35
A
Ω
A
Ω
A
Ω
A
Ω
t
TSSHD
t
RU
t
RL
t
FU
t
FL
t
PDHU
t
PDHL
t
PDLU
t
PDLL
t
PDTS
V
PVCC
= 12V, 3nF Load, 10% to 90%
V
PVCC
= 12V, 3nF Load, 10% to 90%
V
PVCC
= 12V, 3nF Load, 90% to 10%
V
PVCC
= 12V, 3nF Load, 90% to 10%
V
PVCC
= 12V, 3nF Load, Adaptive
V
PVCC
= 12V, 3nF Load, Adaptive
V
PVCC
= 12V, 3nF Load
V
PVCC
= 12V, 3nF Load
V
PVCC
= 12V, 3nF Load
Recommended Operating Conditions, Unless Otherwise Noted.
(Continued)
SYMBOL
TEST CONDITIONS
VCC = 12V
MIN
-
-
-
-
-
-
-
-
-
-
-
TYP
1.96
245
26
18
18
12
10
10
10
10
10
MAX
-
-
-
-
-
-
-
-
-
-
-
UNITS
V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R
L_SOURCE
150mA Source Current
I
L_SINK
R
L_SINK
V
PVCC
= 12V, 3nF Load
150mA Sink Current
Functional Pin Description
PACKAGE PIN #
SOIC
1
2
DFN
1
2
PIN
SYMBOL
UGATE
BOOT
FUNCTION
Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal Bootstrap
Device section under DESCRIPTION for guidance in choosing the capacitor value.
No Connection.
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see
the three-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output of the
controller.
Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
Connect this pin to a +12V bias supply. Place a high quality low ESR ceramic capacitor from this pin to GND.
This pin supplies power to both upper and lower gate drives in PX3511B; only the lower gate drive in PX3511A.
Its operating range is +5V to 12V. Place a high quality low ESR ceramic capacitor from this pin to GND.
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
-
3
3,8
4
N/C
PWM
4
5
6
7
8
9
5
6
7
9
10
11
GND
LGATE
VCC
PVCC
PHASE
PAD
5
FN6462.0
February 26, 2007
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