UXN14M9P
14 GHz Divide-by-8 to 511
Programmable Integer Divider
Features
• Wide Operating Range: DC – 14
GHz
• Contiguous Divide Ratios: 8 to 511
• Large Output Swings: >1 Vpp/side
• Single-Ended and/or Differential
Drive
• Size: 6mm x 6mm
• Parallel Control Lines
• Low SSB Phase Noise:
▪ 147 dBc @ 10 kHz Offset
Description
The UXN14M9P is a highly programma-
ble integer divider covering all integer
divide ratios between 8 and 511.
The device features single-ended
or differential inputs and outputs.
Parallel control inputs are CMOS
and LVTTL compatible for ease of
system integration. The UXN14M9P
is packaged in a 40-pin, 6mm x 6mm
leadless plastic surface mount package.
Application
The UXN14M9P can be used as a general
purpose, highly configurable, divider in
a variety of high frequency synthesizer
applications. Fast switching combined with
a wide range of divide ratios make the
UXN14M9P an excellent choice for fraction-
al-N and integer-N PLLs. Fractional division
may be achieved by applying a sequence to
the divider control lines, such as a delta-
sigma modulated sequence.
Pad Metallization
The QFN package pad metallization consists
of a 300-800 micro-inch (typical thickness 435
micro-inch or 11.04um) 100% matte Sn plate.
The plating covers a Cu (C194) leadframe.
The packages are manufactured
with a >1hr 150C annealing/heat treating
process, and the matte (non-glossy) plating,
specifically to mitigate tin whisker growth.
Key Specifications (T = 25˚C):
Vee = -3.3 V, Iee = 185 mA, Zo=50 Ω
Parameter
Fin (GHz)
Pin (dBm)
Pout (dBm)
PDC (W)
θjc (ºC/W)
Description
Input Frequency
Input Power
Output Power
DC Power Dissipation
Junction-Case Thermal Resistance
Min
DC*
-
-
-
-
Typ
-
0
+4
1.1
14
Max
14
+10
-
-
-
* Low frequency limit dependent on input edge speed
SMD-00020 Rev E
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UXN14M9P
Frequency Divider Application
Min/Max Single-Ended Input Power, INP*
Input Sensitivity, T=25º C, Divide-by-10, FRS=0
Min/Max Single-Ended Input Power, INP*
Input Sensitivity, T=25º C, Divide-by-10, FRS=1
Min/Max Single-Ended Input Power, INP*
Input Sensitivity, -3.3 V, Divide-by-10, FRS=0
Min/Max Single-Ended Input Power, INP*
Input Sensitivity, -3.3 V, Divide-by-10, FRS=1
Output Power
Output Power
SMD-00020 Rev E
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UXN14M9P
Functional Block Diagram
Table 1: Pin Description
Port Name
INP
INN
OUTP
OUTN
P0-P8
VCC
VEE
Description
Divider Input, Positive Terminal
Divider Input, Negative Terminal
Divider Output, Positive Terminal
Divider Output, Negative Terminal
Divider Modulus Control (P8=MSB)
RF & DC Ground
-3.3 V @ 340 mA
Notes
CML signal levels
CML signal levels
CML signal levels
CML signal levels
CMOS levels, see Equation 1, defaults to logic 0
The paddle is connected to +VCC inside the package
Negative Supply Voltage
Equation 3:
Divider Modulus = N = P
0
· 2
0
+ P
1
· 2
1
+ P
2
· 2
2
+ ... + P
8
· 2
8
for 8 ≤ N ≤ 511
Simplified Control Logic Schematic
Table 2: CMOS Levels for control line P0-P8
Logic Level
1 (High)
0 (Low)
Minimum
Vcc-1.25 V
Vee
Typical
Vcc-0.8V
Vee
Maximum
Vcc-0.8V
Vee+1.25 V
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UXN14M9P
Application Notes
Low Frequency Operation:
Low frequency operation is limited by external bypass capacitors and the slew rate of the input clock.
The next paragraph shows the calculations for the bypass capacitors. If DC coupled, the device
operates down to DC for square-wave inputs. Sine-wave inputs are limited to ~50 MHz due to the 10
dBm max input power limitation.
The values of the coupling capacitors for the high-speed inputs and outputs (I/O’s) are determined by
the lowest frequency the IC will be operated at.
C>>
1
2•π•50Ω•f
lowest
For example to use the device below 30 kHz, coupling capacitors should be larger than 0.1uF.
IC Assembly:
The device is designed to operate with either single-ended or differential inputs. Figures 1, 2 & 3
show the IC assembly diagrams for positive and negative supply voltages. In either case the sup-
ply should be capacitively bypassed to the ground to provide a good AC ground over the frequency
range of interest. The backside of the chip should be connected to a good thermal heat sink.
All RF I/O’s are connected to VCC through on-chip termination resistors. This implies that when VCC
is not DC grounded (as in the case of positive supply), the RF I/O’s should be AC coupled through
series capacitors unless the connecting circuit can generate the correct levels through level shifting.
ESD Sensitivity:
Although SiGe IC’s have robust ESD sensitivities, preventive ESD measures should be taken while
storing, handling, and assembling.
Inputs are more ESD susceptible as they could expose the base of a BJT or the gate of a MOSFET.
For this reason, all the inputs are protected with ESD diodes. These inputs have been tested to with-
stand voltage spikes up to 400V.
Table 3: CML Logic Levels for DC Coupling (T=25 °C) Assuming 50Ω terminations
at inputs and outputs
Parameter
Differential
Input
Single
Minimum
Typical
Vcc
Vcc - 0.3 V
Vcc + 0.3 V
Vcc - 0.3 V
Vcc – 0.6 V
Vcc – 1.6 V
Maximum
Vcc
Vcc - 1 V
Vcc + 1 V
Vcc - 1 V
Vcc – 0.5 V
Vcc – 1.7 V
{
Logic Input
high
Logic Input
low
Logic Input
high
Logic Input
low
Logic Input
high
Logic Input
low
Vcc
Vcc - 0.05 V
Vcc + 0.05 V
Vcc - 0.05 V
Vcc - 0.9 V
Vcc – 1.1 V
{
{
Output
Differential & Single
MM-PDS-0037 Rev A
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UXN14M9P
Differential vs. Single-Ended:
The UXN14M9P is fully differential to maximize signal-to-noise ratios for high-speed operation. All
high speed inputs and outputs are terminated to Vcc with on-chip resistors (refer to functional block
diagram for specific resistor values). The maximum DC voltage on any terminal must be limited to
Vcc +/- 1V to prevent damaging the termination resistors with excessive current. Regardless of bias
conditions, the following equation should be satisfied when driving the inputs differentially:
VCC -1 < VAC/4 + VDC < VCC +1
where VAC is the input signal p-p voltage and VDC is common-mode voltage.
The outputs require a DC return path capable of handling ~30mA per side. If DC coupling is
employed, the DC resistance of the receiving circuits should be 50 ohms to Vcc. If AC coupling
is used, a bias tee circuit should be used such as shown below. The discrete R/L/C elements should
be resonance free up to the maximum frequency of operation for broadband applications.
In addition to the maximum input signal levels, single-ended operation imposes additional restrictions:
the average DC value of the waveform at IC should be equal to Vcc for single-ended operation.
In practice, this is easily achieved with a single capacitor on the input acting as a DC block. The value
of the capacitor should be large enough to pass the lowest frequencies of interest.
Note that a potential oscillation mechanism exists if both inputs are static and have identical
DC voltages; a small DC offset on either input is sufficient to prevent possible oscillations
Connecting a 10k ohm resistor between the unused input and Vee should provide sufficient offset
to prevent oscillation.
MM-PDS-0037 Rev A
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