in the United States and other countries. AMBA, AMBA Designer, ARM, ARM Cortex-A9, CoreSight, Cortex, and PrimeCell are trademarks of ARM in the EU and other countries.
PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS190 (v1.11.1) July 2, 2018
Product Specification
www.xilinx.com
1
Zynq-7000 SoC Data Sheet: Overview
Programmable Logic (PL)
Configurable Logic Blocks (CLB)
•
•
•
Look-up tables (LUT)
Flip-flops
Cascadeable adders
JTAG Boundary-Scan
•
IEEE Std 1149.1 Compatible Test Interface
PCI Express® Block
•
•
•
Supports Root complex and End Point configurations
Supports up to Gen2 speeds
Supports up to 8 lanes
36 Kb Block RAM
•
•
•
True Dual-Port
Up to 72 bits wide
Configurable as dual 18 Kb block RAM
Serial Transceivers
•
•
Up to 16 receivers and transmitters
Supports up to 12.5 Gb/s data rates
DSP Blocks
•
•
•
18 x 25 signed multiply
48-bit adder/accumulator
25-bit pre-adder
Two 12-Bit Analog-to-Digital Converters
•
•
•
On-chip voltage and temperature sensing
Up to 17 external differential input channels
One million samples per second maximum conversion rate
Programmable I/O Blocks
•
•
•
Supports LVCMOS, LVDS, and SSTL
1.2V to 3.3V I/O
Programmable I/O delay and SerDes
Feature Summary
Table 1:
Zynq-7000 and Zynq-7000S SoCs
Device Name
Part Number
Processor Core
Processor Extensions
Maximum Frequency
L1 Cache
Processing System
L2 Cache
On-Chip Memory
External Memory
Support
(1)
External Static Memory
Support
(1)
DMA Channels
Peripherals
(1)
Peripherals w/
built-in DMA
(1)
Security
(2)
Processing System to
Programmable Logic
Interface Ports
(Primary Interfaces &
Interrupts Only)
Z-7007S
XC7Z007S
Z-7012S
XC7Z012S
Z-7014S
XC7Z014S
Z-7010
XC7Z010
Z-7015
XC7Z015
Z-7020
XC7Z020
Z-7030
XC7Z030
Z-7035
XC7Z035
Z-7045
XC7Z045
Z-7100
XC7Z100
Single-core ARM Cortex-A9
MPCore™ with CoreSight™
Dual-core ARM Cortex-A9 MPCore™ with CoreSight™
NEON™ & Single / Double Precision Floating Point for each processor
667 MHz (-1); 766 MHz (-2)
667 MHz (-1); 766 MHz (-2); 866 MHz (-3)
667 MHz (-1); 800 MHz (-2); 1 GHz (-3)
667 MHz (-1)
800 MHz (-2)
32 KB Instruction, 32 KB data per processor
512 KB
256 KB
DDR3, DDR3L, DDR2, LPDDR2
2x Quad-SPI, NAND, NOR
8 (4 dedicated to Programmable Logic)
2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO
2x USB 2.0 (OTG), 2x Tri-mode Gigabit Ethernet, 2x SD/SDIO
RSA Authentication, and AES and SHA 256-bit Decryption and Authentication for Secure Boot
2x AXI 32b Master 2x AXI 32-bit Slave
4x AXI 64-bit/32-bit Memory
AXI 64-bit ACP
16 Interrupts
DS190 (v1.11.1) July 2, 2018
Product Specification
www.xilinx.com
2
Zynq-7000 SoC Data Sheet: Overview
Table 1:
Zynq-7000 and Zynq-7000S SoCs
(Cont’d)
Device Name
Part Number
Xilinx 7 Series
Programmable Logic
Equivalent
Programmable Logic
Cells
Look-Up Tables (LUTs)
Programmable Logic
Flip-Flops
Block RAM
(# 36 Kb Blocks)
DSP Slices
(18x25 MACCs)
Peak DSP
Performance
(Symmetric FIR)
PCI Express
(Root Complex or
Endpoint)
(3)
Analog Mixed Signal
(AMS) / XADC
Security
(2)
Z-7007S
XC7Z007S
Artix®-7
FPGA
23K
14,400
28,800
1.8 Mb
(50)
66
73
GMACs
Z-7012S
XC7Z012S
Artix-7
FPGA
55K
34,400
68,800
2.5 Mb
(72)
120
131
GMACs
Z-7014S
XC7Z014S
Artix-7
FPGA
65K
40,600
81,200
3.8 Mb
(107)
170
187
GMACs
Z-7010
XC7Z010
Artix-7
FPGA
28K
17,600
35,200
2.1 Mb
(60)
80
100
GMACs
Z-7015
XC7Z015
Artix-7
FPGA
74K
46,200
92,400
3.3 Mb
(95)
160
200
GMACs
Z-7020
XC7Z020
Artix-7
FPGA
85K
53,200
106,400
4.9 Mb
(140)
220
276
GMACs
Z-7030
XC7Z030
Kintex®-7
FPGA
125K
78,600
157,200
9.3 Mb
(265)
400
593
GMACs
Z-7035
XC7Z035
Kintex-7
FPGA
275K
171,900
343,800
17.6 Mb
(500)
900
1,334
GMACs
Z-7045
XC7Z045
Kintex-7
FPGA
350K
218,600
437,200
19.2 Mb
(545)
900
1,334
GMACs
Z-7100
XC7Z100
Kintex-7
FPGA
444K
277,400
554,800
26.5 Mb
(755)
2,020
2,622
GMACs
Gen2 x4
Gen2 x4
Gen2 x4
Gen2 x8
Gen2 x8
Gen2 x8
2x 12 bit, MSPS ADCs with up to 17 Differential Inputs
AES and SHA 256b for Boot Code and Programmable Logic Configuration, Decryption, and Authentication
Notes:
1. Restrictions apply for CLG225 package. Refer to the
UG585,
Zynq-7000 SoC Technical Reference Manual
(TRM) for details.
2. Security is shared by the Processing System and the Programmable Logic.
3. Refer to
PG054,
7 Series FPGAs Integrated Block for PCI Express
for PCI Express support in specific devices.
DS190 (v1.11.1) July 2, 2018
Product Specification
www.xilinx.com
3
Zynq-7000 SoC Data Sheet: Overview
Table 2:
Device-Package Combinations: Maximum I/Os and GTP and GTX Transceivers
Package
(1)
Size
Ball Pitch
Transceiver
Speed (max)
Device
XC7Z007S
XC7Z012S
XC7Z014S
XC7Z010
XC7Z015
XC7Z020
XC7Z030
XC7Z035
XC7Z045
XC7Z100
Notes:
1. All packages listed are Pb-free (SBG485 with exemption 15). Some packages are available with a Pb option.
2. The Z-7012S and Z-7015 devices in the CLG485 package and the Z-7030 device in the SBG485 package are pin-to-pin compatible.
3. PS I/O count does not include dedicated DDR calibration pins.
4. HR = High Range I/O with support for I/O voltage from 1.2V to 3.3V.
5. HP = High Performance I/O with support for I/O voltage from 1.2V to 1.8V.
128
125
–
128
200
–
128
4
50
100
84
54
–
128
128
125
100
–
–
128
4
150
–
128
200
–
PS I/O
(3)
84
SelectIO
HR
(4)
54
HP
(5)
–
PS I/O
(3)
128
SelectIO
HR
(4)
100
HP
(5)
–
128
4
150
–
PS I/O
(3)
SelectIO
HR
(4)
HP
(5)
PS I/O
(3)
CLG225
13 x 13 mm
0.8 mm
CLG400
17 x 17 mm
0.8 mm
CLG484
19 x 19 mm
0.8 mm
CLG485
(2)
19 x 19 mm
0.8 mm
6.25 Gb/s
SelectIO
GTP
HR
(4)
HP
(5)
PS I/O
(3)
SBG485
(2)
19 x 19 mm
0.8 mm
6.6 Gb/s
SelectIO
GTX
HR
(4)
HP
(5)
Table 3:
Device-Package Combinations: Maximum I/Os and GTP and GTX Transceivers
(Cont’d)
Package
(1)
Size
Ball Pitch
Transceiver
Speed (max)
Device
XC7Z007S
XC7Z012S
XC7Z014S
XC7Z010
XC7Z015
XC7Z020
XC7Z030
XC7Z035
XC7Z045
XC7Z100
128
4
100
63
128
128
128
4
8
8
100
100
100
150
150
150
128
128
128
4
8
8
100
100
100
150
150
150
128
128
128
16
16
16
212
212
212
150
150
150
128
16
250
150
FBG484
23 x 23 mm
1.0 mm
6.6 Gb/s
PS I/O
(2)
GTX
SelectIO
HR
(3)
HP
(4)
FBG676
27 x 27 mm
1.0 mm
6.6 Gb/s
PS I/O
(2)
GTX
SelectIO
HR
(3)
HP
(4)
FFG676
27 x 27 mm
1.0 mm
12.5 Gb/s
PS I/O
(2)
GTX
SelectIO
HR
(3)
HP
(4)
FFG900
31 x 31 mm
1.0 mm
12.5 Gb/s
PS I/O
(2)
GTX
SelectIO
HR
(3)
HP
(4)
FFG1156
35 x 35 mm
1.0 mm
10.3 Gb/s
PS I/O
(2)
GTX
SelectIO
HR
(3)
HP
(4)
Notes:
1. All packages listed are Pb-free (FBG and FFG with exemption 15). Some packages are available with a Pb option.
2. PS I/O count does not include dedicated DDR calibration pins.
3. HR = High Range I/O with support for I/O voltage from 1.2V to 3.3V.
4. HP = High Performance I/O with support for I/O voltage from 1.2V to 1.8V.
DS190 (v1.11.1) July 2, 2018
Product Specification
www.xilinx.com
4
Zynq-7000 SoC Data Sheet: Overview
Zynq-7000 Family Description
The Zynq-7000 family offers the flexibility and scalability of an FPGA, while providing performance, power, and ease of use
typically associated with ASIC and ASSPs. The range of devices in the Zynq-7000 family allows designers to target
cost-sensitive as well as high-performance applications from a single platform using industry-standard tools. While each
device in the Zynq-7000 family contains the same PS, the PL and I/O resources vary between the devices. As a result, the
Zynq-7000 and Zynq-7000S SoCs are able to serve a wide range of applications including:
•
•
•
•
•
•
•
•
Automotive driver assistance, driver information, and infotainment
Broadcast camera
Industrial motor control, industrial networking, and machine vision
IP and Smart camera
LTE radio and baseband
Medical diagnostics and imaging
Multifunction printers
Video and night vision equipment
The Zynq-7000 architecture enables implementation of custom logic in the PL and custom software in the PS. It allows for
the realization of unique and differentiated system functions. The integration of the PS with the PL allows levels of
performance that two-chip solutions (e.g., an ASSP with an FPGA) cannot match due to their limited I/O bandwidth, latency,
and power budgets.
Xilinx offers a large number of soft IP for the Zynq-7000 family. Stand-alone and Linux device drivers are available for the
peripherals in the PS and the PL. The Vivado® Design Suite development environment enables a rapid product
development for software, hardware, and systems engineers. Adoption of the ARM-based PS also brings a broad range of
third-party tools and IP providers in combination with Xilinx’s existing PL ecosystem.
The inclusion of an application processor enables high-level operating system support, e.g., Linux. Other standard operating
systems used with the Cortex-A9 processor are also available for the Zynq-7000 family.
The PS and the PL are on separate power domains, enabling the user of these devices to power down the PL for power
management if required. The processors in the PS always boot first, allowing a software centric approach for PL
configuration. PL configuration is managed by software running on the CPU, so it boots similar to an ASSP.
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