W25Q512JV-DTR
3.0V 512M-BIT
SERIAL FLASH MEMORY WITH
DUAL/QUAD SPI, QPI & DTR
Publication Release Date: June 29, 2020
-Revision D
W25Q512JV-DTR
Table of Contents
1.
2.
3.
GENERAL DESCRIPTIONS ............................................................................................................. 5
FEATURES ....................................................................................................................................... 5
PACKAGE TYPES AND PIN CONFIGURATIONS........................................................................... 6
3.1
3.2
3.3
3.4
3.5
3.6
4.
4.1
4.2
4.3
4.4
4.5
4.6
5.
6.
Pad Configuration 8x6-mm ................................................................................................... 6
Pad Description 8x6-mm ...................................................................................................... 6
Pin Configuration SOIC 300-mil ........................................................................................... 7
Pin Description SOIC 300-mil ............................................................................................... 7
Ball Configuration TFBGA 8x6-mm (5x5 Ball Array) ............................................................ 8
Ball Description TFBGA 8x6-mm ......................................................................................... 8
Chip Select (/CS) .................................................................................................................. 9
Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) ..................................... 9
Write Protect (/WP) .............................................................................................................. 9
HOLD (/HOLD) ..................................................................................................................... 9
Serial Clock (CLK) ................................................................................................................ 9
Reset (/RESET) .................................................................................................................... 9
PIN DESCRIPTIONS ........................................................................................................................ 9
BLOCK DIAGRAM .......................................................................................................................... 10
FUNCTIONAL DESCRIPTIONS ..................................................................................................... 11
6.1
SPI / QPI Operations .......................................................................................................... 11
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
Standard SPI Instructions ..................................................................................................... 11
Dual SPI Instructions ............................................................................................................ 11
Quad SPI Instructions ........................................................................................................... 12
QPI Instructions .................................................................................................................... 12
SPI / QPI DTR Read Instructions ......................................................................................... 12
3-Byte / 4-Byte Address Modes ............................................................................................ 12
Hold Function ....................................................................................................................... 13
Software Reset & Hardware /RESET pin .............................................................................. 13
6.2
7.
7.1
Write Protection .................................................................................................................. 14
Status Registers ................................................................................................................. 15
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
Program/Erase/Write In Progress (BUSY)
–
Status Only
.................................................. 15
Write Enable Latch (WEL)
–
Status Only
.......................................................................... 15
Block Protect Bits (BP3, BP2, BP1, BP0)
–
Volatile/Non-Volatile Writable
....................... 16
Top/Bottom Block Protect (TB)
–
Volatile/Non-Volatile Writable
....................................... 16
Complement Protect (CMP)
–
Volatile/Non-Volatile Writable
............................................ 16
Status Register Protect (SRP, SRL)
–
Volatile/Non-Volatile Writable
............................... 16
Erase/Program Suspend Status (SUS)
–
Status Only.......................................................
17
STATUS AND CONFIGURATION REGISTERS ............................................................................ 15
-1-
W25Q512JV-DTR
7.1.8 Security Register Lock Bits (LB3, LB2, LB1, SFDP Lock bit)
–
Volatile/Non-Volatile OTP
Writable
............................................................................................................................................. 17
7.1.9
7.1.10
7.1.11
7.1.12
7.1.13
7.1.14
7.1.15
7.1.16
7.1.17
7.1.18
Quad Enable (QE)
–
Volatile/Non-Volatile Writable
.......................................................... 17
Current Address Mode (ADS)
–
Status Only
................................................................... 18
Power-Up Address Mode (ADP)
–
Non-Volatile Writable
................................................ 18
Write Protect Selection (WPS)
–
Volatile/Non-Volatile Writable
..................................... 18
Output Driver Strength (DRV1, DRV0)
–
Volatile/Non-Volatile Writable
......................... 19
/HOLD or /RESET Pin Function (HOLD/RST)
–
Volatile/Non-Volatile Writable
.............. 19
Reserved Bits
–
Non Functional
...................................................................................... 19
W25Q512JV Status Register Memory Protection (WPS = 0, CMP = 0) ............................. 20
W25Q512JV Status Register Memory Protection (WPS = 0, CMP = 1) ............................. 21
W25Q512JV Individual Block Memory Protection (WPS=1) .............................................. 22
7.2
8.
Extended Address Register
–
Volatile Writable Only
...................................................... 23
INSTRUCTIONS ............................................................................................................................. 24
8.1
Device ID and Instruction Set Tables ................................................................................. 24
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.1.7
8.1.8
8.1.9
8.1.10
8.1.11
Manufacturer and Device Identification ................................................................................ 24
Instruction Set Table 1 (Standard/Dual/Quad SPI, 3-Byte Address Mode ADS=0)
(1)
........... 25
Instruction Set Table 2 (Dual/Quad SPI Instructions,3-Byte Address Mode ADS=0) ........... 26
Instruction Set Table 3 (Standard SPI, 4-Byte Address Mode ADS=1)
(1)
............................. 27
Instruction Set Table 4 (Dual/Quad SPI Instructions, 4-Byte Address Mode ADS=1) .......... 28
Instruction Set Table 5 (QPI Instructions, 3-Byte Address Mode) ........................................ 29
Instruction Set Table 6 (QPI Instructions, 4-Byte Address Mode) ........................................ 30
Instruction Set Table 7 (DTR with SPI Instructions, 3-Byte Address Mode) ......................... 31
Instruction Set Table 8 (DTR with SPI Instructions, 4-Byte Address Mode) ......................... 31
Instruction Set Table 9 (DTR with QPI Instructions, 3-Byte Address Mode)....................... 31
Instruction Set Table 10 (DTR with QPI Instructions, 4-Byte Address Mode)..................... 31
Notes:................................................................................................................................................ 32
8.2
Instruction Descriptions ...................................................................................................... 33
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
8.2.10
8.2.11
8.2.12
8.2.13
8.2.14
Write Enable (06h) ............................................................................................................... 33
Write Enable for Volatile Status Register (50h) .................................................................... 33
Write Disable (04h) ............................................................................................................... 34
Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h) .............. 34
Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h) .............. 35
Read Extended Address Register (C8h) .............................................................................. 38
Write Extended Address Register (C5h) .............................................................................. 39
Enter 4-Byte Address Mode (B7h) ........................................................................................ 40
Exit 4-Byte Address Mode (E9h) .......................................................................................... 40
Read Data (03h) ................................................................................................................. 41
Read Data with 4-Byte Address (13h) ................................................................................ 42
Fast Read (0Bh) ................................................................................................................. 43
DTR Fast Read (0Dh) ......................................................................................................... 45
Fast Read with 4-Byte Address (0Ch) ................................................................................ 47
-2-
Publication Release Date: June 29, 2020
-Revision D
W25Q512JV-DTR
8.2.15
8.2.16
8.2.17
8.2.18
8.2.19
8.2.20
8.2.21
8.2.22
8.2.23
8.2.24
8.2.25
8.2.26
8.2.27
8.2.28
8.2.29
8.2.30
8.2.31
8.2.32
8.2.33
8.2.34
8.2.35
8.2.36
8.2.37
8.2.38
8.2.39
8.2.40
8.2.41
8.2.42
8.2.43
8.2.44
8.2.45
8.2.46
8.2.47
8.2.48
8.2.49
8.2.50
8.2.51
8.2.52
8.2.53
8.2.54
8.2.55
8.2.56
8.2.57
Fast Read Dual Output (3Bh) ............................................................................................. 48
Fast Read Dual Output with 4-Byte Address (3Ch) ............................................................ 49
Fast Read Quad Output (6Bh) ............................................................................................ 50
Fast Read Quad Output with 4-Byte Address (6Ch) ........................................................... 51
Fast Read Dual I/O (BBh) ................................................................................................... 52
DTR Fast Read Dual I/O (BDh) .......................................................................................... 54
Fast Read Dual I/O with 4-Byte Address (BCh) .................................................................. 56
Fast Read Quad I/O (EBh) ................................................................................................. 58
DTR Fast Read Quad I/O (EDh) ......................................................................................... 61
Fast Read Quad I/O with 4-Byte Address (ECh) ................................................................ 64
Set Burst with Wrap (77h) .................................................................................................. 66
Page Program (02h) ........................................................................................................... 67
Page Program with 4-Byte Address (12h) .......................................................................... 69
Quad Input Page Program (32h) ........................................................................................ 70
Quad Input Page Program with 4-Byte Address (34h) ....................................................... 71
Sector Erase (20h) ............................................................................................................. 72
Sector Erase with 4-Byte Address (21h)............................................................................. 73
32KB Block Erase (52h) ..................................................................................................... 74
64KB Block Erase (D8h) ..................................................................................................... 75
64KB Block Erase with 4-Byte Address (DCh) ................................................................... 76
Chip Erase (C7h / 60h) ....................................................................................................... 77
Erase / Program Suspend (75h) ......................................................................................... 78
Erase / Program Resume (7Ah) ......................................................................................... 80
Power-down (B9h) .............................................................................................................. 81
Release Power-down / Device ID (ABh) ............................................................................. 82
Read Manufacturer / Device ID (90h) ................................................................................. 84
Read Manufacturer / Device ID Dual I/O (92h) ................................................................... 85
Read Manufacturer / Device ID Quad I/O (94h) ................................................................. 86
Read Unique ID Number (4Bh)........................................................................................... 87
Read JEDEC ID (9Fh) ........................................................................................................ 88
Read SFDP Register (5Ah) ................................................................................................ 89
Erase Security Registers (44h) ........................................................................................... 90
Program Security Registers (42h) ...................................................................................... 91
Read Security Registers (48h) ........................................................................................... 92
Set Read Parameters (C0h) ............................................................................................... 93
Burst Read with Wrap (0Ch)............................................................................................... 94
DTR Burst Read with Wrap (0Eh) ...................................................................................... 95
Enter QPI Mode (38h)......................................................................................................... 96
Exit QPI Mode (FFh) ........................................................................................................... 97
Individual Block/Sector Lock (36h) ..................................................................................... 98
Individual Block/Sector Unlock (39h) .................................................................................. 99
Read Block/Sector Lock (3Dh) ......................................................................................... 100
Global Block/Sector Lock (7Eh) ........................................................................................ 101
-3-
W25Q512JV-DTR
8.2.58
8.2.59
Global Block/Sector Unlock (98h) ..................................................................................... 101
Enable Reset (66h) and Reset Device (99h) .................................................................... 102
9.
ELECTRICAL CHARACTERISTICS ............................................................................................. 103
9.1
Absolute Maximum Ratings (1) ........................................................................................ 103
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
Operating Ranges............................................................................................................. 103
Power-up Power-down Timing and Requirements ........................................................... 104
DC Electrical Characteristics ............................................................................................ 105
AC Measurement Conditions ............................................................................................ 106
AC Electrical Characteristics ............................................................................................ 107
Serial Output Timing ......................................................................................................... 109
Serial Input Timing ............................................................................................................ 109
/HOLD Timing ................................................................................................................... 109
/WP Timing ....................................................................................................................... 109
8-Pad WSON 8x6-mm (Package Code E) ....................................................................... 110
16-Pin SOIC 300-mil (Package Code F) .......................................................................... 111
24-Ball TFBGA 8x6-mm (Package Code B, 5x5-1 Ball Array) ......................................... 112
Ordering Information ......................................................................................................... 113
Valid Part Numbers and Top Side Marking ...................................................................... 114
10.
PACKAGE SPECIFICATIONS ...................................................................................................... 110
10.1
10.2
10.3
10.4
10.5
11.
REVISION HISTORY .................................................................................................................... 115
-4-
Publication Release Date: June 29, 2020
-Revision D
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