SL28PCIe10
EProClock
®
PCI-Express Gen 2 Clock Generator
Features
• One Programmable Spreadable Single-ended Clock
• PCI-Express Gen 2 Compliant
• Low power push-pull type differential output buffers
• Integrated voltage regulator
• Integrated resistors on differential clocks
• Scalable low voltage VDD_IO (3.3V to 1.05V)
• Wireless friendly 3-bits slew rate control on
single-ended clocks.
• Four 100MHz Differential clocks
• 27MHz Video clock
• Buffered Reference Clock 25MHz
• EProClock
®
Programmable Technology
• I
2
C support with readback capabilities
• Triangular Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• Industrial Temperature -40
o
C to 85
o
C
• 3.3V Power supply
• 32-pin QFN package
100Mhz
x4
48M
x1
REF 27M
x1
x1
Programmable
Single-ended Clock
x1
Block Diagram
Pin Configuration
32 31 30 29 28 27 26 25
VDD
1
VSS
2
NC
3
NC
4
VDD_27
5
27M_NSS
6
Prog_SE
7
VSS_27
8
9 10 11 12 13 14 15 16
SRC0
SRC0#
SRC1
SRC1#
VDD_SRC_IO
VSS_SRC
VSS_SRC
OE#_SRC2_SRC3
24
VDD_SRC
23
SRC3
22
SRC3#
SL28PCIe10
21
VSS_SRC
20
SRC2
19
SRC2#
18
VDD_SRC_IO
17
VDD_SRC
....................................... Document #: Rev 1.1 Page 1 of 16
400 West Cesar Chavez, Austin, TX 78701
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1+(512) 416-9669
www.silabs.com
CKPWRGD/PD#
VSS_REF
VDD_REF
SCLOCK
SDATA
XOUT
REF
XIN
SL28PCIe10
32-QFN Pin Definitions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VDD
VSS
NC
NC
VDD_27
27M_NSS
Prog_SE
VSS_27
VSS_SRC
SRC0
SRC0#
VSS_SRC
SRC1
SRC1#
VDD_SRC_IO
OE#_SRC2_SRC3
VDD_SRC
VDD_SRC_IO
SRC2#
SRC2
VSS_SRC
SRC3#
SRC3
VDD_SRC
CK_PWRGD/PD#
VSS_REF
XOUT
XIN
VDD_REF
REF
SDATA
SCLK
Name
Type
PWR
GND
NC
NC
PWR
O,SE
GND
GND
Description
3.3V Power supply
Ground
No Connect.
No Connect.
3.3V Power supply
Non-spread 27MHz video clock output
Ground
Ground
O, SE Spreadable Programmable Single-Ended clock output
O, DIF 100MHz True differential serial reference clock
O, DIF 100MHz Complement differential serial reference clock
GND
Ground
O, DIF 100MHz True differential serial reference clock
O, DIF 100MHz Complement differential serial reference clock
PWR
I
PWR
PWR
Scalable 3.3V to 1.05V power supply for output buffer
3.3V tolerance input to disable Output on Pin 7 and Pin 8
3.3V Power supply
Scalable 3.3V to 1.05V power supply for output buffer
O, DIF 100MHz True differential serial reference clock
O, DIF 100MHz Complement differential serial reference clock
GND
Ground
O, DIF 100MHz True differential serial reference clock
O, DIF 100MHz Complement differential serial reference clock
PWR
I
GND
I
PWR
3.3V Power supply
3.3V LVTTL input. After CK_PWRGD (active HIGH) assertion, this pin becomes a
real-time input for asserting power down (active LOW)
Ground
25MHz Crystal input
3.3V Power supply for outputs and also maintains SMBUS registers during
power-down
SMBus compatible SDATA
SMBus compatible SCLOCK
O, SE 25MHz Crystal output
PD, I/O Reference 25MHz clock output
I/O
I
Programmable Single ended clock
SL28PCIe10 allows flexibility of programming any frequency
at single ended output Prog_SE.
Prog_SE can be factory programmed to any frequency as
required by the end user with a 3.3V swing single ended
output. This clock can have a feature of Spread Spectrum to
reduce EMI.
.......................................Document #: Rev 1.1 Page 2 of 16
SL28PCIe10
EProClock
®
Programmable Technology
EProClock
®
is the world’s first non-volatile programmable
clock. The EProClock
®
technology allows board designer to
promptly achieve optimum compliance and clock signal
integrity; historically, attainable typically through device and/or
board redesigns.
EProClock
®
technology can be configured through SMBus or
hard coded.
Features:
- > 4000 bits of configurations
- Can be configured through SMBus or hard coded
- Custom frequency sets
- Differential skew control on true or compliment or both
- Differential duty cycle control on true or compliment or both
- Differential amplitude control
- Differential and single-ended slew rate control
- Program Internal or External series resistor on single-ended
clocks
- Program different spread profiles
- Program different spread modulation rate
.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in
Table 1.
The block write and block read protocol is outlined in
Table 2
while
Table 3
outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h).
Table 1. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
36:29
37
45:38
46
....
....
....
....
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Byte Count–8 bits
Acknowledge from slave
Data byte 1–8 bits
Acknowledge from slave
Data byte 2–8 bits
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N–8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
46:39
47
55:48
56
....
....
....
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeat start
Slave address–7 bits
Read = 1
Acknowledge from slave
Byte Count from slave–8 bits
Acknowledge
Data byte 1 from slave–8 bits
Acknowledge
Data byte 2 from slave–8 bits
Acknowledge
Data bytes from slave / Acknowledge
Data Byte N from slave–8 bits
NOT Acknowledge
Block Read Protocol
Description
.......................................Document #: Rev 1.1 Page 3 of 16
SL28PCIe10
Table 2. Block Read and Block Write Protocol
(continued)
Block Write Protocol
Bit
Description
Bit
....
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
29
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Data byte–8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
39
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeated start
Slave address–7 bits
Read
Acknowledge from slave
Data from slave–8 bits
NOT Acknowledge
Stop
Byte Read Protocol
Description
Stop
Block Read Protocol
Description
.......................................Document #: Rev 1.1 Page 4 of 16
SL28PCIe10
Control Registers
Byte 0: Control Register 0
Bit
7
6
5
4
3
2
1
0
@Pup
HW
0
1
0
0
0
0
1
Name
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
PD_Restore
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Save configuration when PD# is asserted
0 = Config. cleared, 1 = Config. saved
Description
Byte 1: Control Register 1
Bit
7
6
5
4
3
2
1
0
@Pup
1
0
0
0
0
1
0
1
Name
RESERVED
PLL1_SS_DC
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Select for down or center SS
0 = Down spread, 1 = Center spread
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Description
Byte 2: Control Register 2
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
REF_OE
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Description
Output enable for REF
0 = Output Disabled, 1 = Output Enabled
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Byte 3: Control Register 3
Bit
7
6
5
4
3
2
1
@Pup
1
1
1
1
1
1
1
Name
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Description
.......................................Document #: Rev 1.1 Page 5 of 16
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