DATASHEET
X28HC64
64k, 8k x 8-Bit 5 Volt, Byte Alterable EEPROM
The
X28HC64
is an 8k x 8 EEPROM, fabricated with Intersil’s
proprietary, high performance, floating gate CMOS technology.
Like all Intersil programmable nonvolatile memories, the
X28HC64 is a 5V only device. It features the JEDEC approved
pinout for byte-wide memories, compatible with industry
standard RAMs.
The X28HC64 supports a 64-byte page write operation, effectively
providing a 32µs/byte write cycle, and enabling the entire
memory to be typically written in 0.25 seconds. The X28HC64
also features DATA Polling and Toggle Bit Polling, two methods
providing early end of write detection. In addition, the X28HC64
includes a user-optional software data protection mode that
further enhances Intersil’s hardware write protect capability.
Intersil EEPROMs are designed and tested for applications
requiring extended endurance. Inherent data retention is
greater than 100 years.
FN8109
Rev 4.00
June 27, 2016
Features
• 70ns access time
• Simple byte and page write
- Single 5V supply
- No external high voltages or V
P-P
control circuits
- Self-timed
- No erase before write
- No complex programming algorithms
- No overerase problem
• Low power CMOS
- 40mA active current maximum
• 200µA standby current maximum
• Fast write cycle times
- 64-byte page write operation
- Byte or page write cycle: 2ms typical
- Complete memory rewrite: 0.25s typical
- Effective byte write cycle time: 32µs typical
• Software data protection
• End of write detection
- DATA polling
- Toggle bit
• High reliability
- Endurance: 100,000 cycles
- Data retention: 100 years
• JEDEC approved byte-wide pinout
• Pb-free available (RoHS compliant)
Pin Configurations
X28HC64
(28 LD PDIP, SOIC)
TOP VIEW
NC
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
X28HC64
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
NC
A
8
A
9
A
11
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
A
7
X28HC64
(32 LD PLCC)
TOP VIEW
V
CC
WE
A
12
NC
NC
NC
29
28
27
X28HC64
26
25
24
23
4 3
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
I/O
0
5
6
7
8
9
10
11
2 1 32 31 30
A
8
A
9
A
11
NC
OE
A
10
CE
I/O
7
I/O
6
22
12
21
13
14 15 16 17 18 19 20
I/O
1
I/O
2
V
SS
NC
I/O
3
I/O
4
I/O
5
FN8109 Rev 4.00
June 27, 2016
Page 1 of 18
X28HC64
Ordering Information
PART NUMBER
X28HC64J-70 (Notes
1, 6)
(No longer available, recommended
replacement: X28HC64JZ-70)
X28HC64JIZ-70 (Notes
1, 4, 6)
X28HC64JZ-70 (Notes
1, 4, 6)
X28HC64SIZ-70 (Notes
4, 6)
X28HC64SZ-70 (Notes
4, 6)
X28HC64J-90 (Notes
1, 6)
(No longer available, recommended
replacement: X28HC64JIZ-90)
X28HC64JI-90 (Notes
1, 3, 6)
(No longer available, recommended
replacement: X28HC64JIZ-90)
X28HC64JIZ-90 (Notes
1, 4, 6)
X28HC64PIZ-90 (Notes
4, 5)
X28HC64PZ-90 (Notes
4, 5)
X28HC64J-12 (Notes
1, 6)
(No longer available, recommended
replacement: X28HC64JZ-12)
X28HC64JI-12 (Notes
1, 6)
(No longer available, recommended
replacement: X28HC64JIZ-12)
X28HC64JIZ-12 (Notes
1, 4, 6)
X28HC64JZ-12* (Notes
1, 4, 6)
X28HC64PIZ-12 (Notes
4, 5)
X28HC64PZ-12 (Notes
4, 5)
X28HC64SIZ-12 (Notes
2, 4, 6)
X28HC64SZ-12 (Notes
4, 6)
NOTES:
1. Add “T1” suffix for 750 unit tape and reel option.
2. Add “T1” suffix for 1000 unit tape and reel option.
3. Add “T2” suffix for 750 unit tape and reel option.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
5. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
6. For Moisture Sensitivity Level (MSL), please see product information page for
X28HC64.
For more information on MSL, please see tech brief
TB363.
PART MARKING
X28HC64J-70 CY
TEMPERATURE
RANGE (°C)
0 to +70
ACCESS TIME
(ns)
70
PACKAGE
32 Ld PLCC
PKG.
DWG. #
N32.45x55
X28HC64JI-70 ZCY
X28HC64J-70 ZCY
X28HC64SI-70 CYZ
X28HC64S-70 CYZ
X28HC64J-90 CY
-40 to +85
0 to +70
-40 to +85
0 to +70
0 to +70
90
32 Ld PLCC (RoHS Compliant)
32 Ld PLCC (RoHS Compliant)
28 Ld SOIC (300 mil) (RoHS
Compliant)
28 Ld SOIC (300 mil) (RoHS
Compliant)
32 Ld PLCC
N32.45x55
N32.45x55
M28.3
M28.3
N32.45x55
X28HC64JI-90 CY
-40 to +85
32 Ld PLCC
N32.45x55
X28HC64JI-90 ZCY
X28HC64PI-90 CYZ
X28HC64P-90 CYZ
X28HC64J-12 CY
-40 to +85
-40 to +85
0 to +70
0 to +70
120
32 Ld PLCC (RoHS Compliant)
28 Ld PDIP (RoHS Compliant)
28 Ld PDIP (RoHS Compliant)
32 Ld PLCC
N32.45x55
E28.6
E28.6
N32.45x55
X28HC64JI-12 CY
-40 to +85
32 Ld PLCC
N32.45x55
X28HC64JI-12 ZCY
X28HC64J-12 ZCY
X28HC64PI-12 CYZ
X28HC64P-12 CYZ
X28HC64SI-12 CYZ
X28HC64S-12 CYZ
-40 to +85
0 to +70
-40 to +85
0 to +70
-40 to +85
0 to +70
32 Ld PLCC (RoHS Compliant)
32 Ld PLCC (RoHS Compliant)
28 Ld PDIP (RoHS Compliant)
28 Ld PDIP (RoHS Compliant)
28 Ld SOIC (300 mil) (RoHS
Compliant)
28 Ld SOIC (300 mil) (RoHS
Compliant)
N32.45x55
N32.45x55
E28.6
E28.6
M28.3
M28.3
FN8109 Rev 4.00
June 27, 2016
Page 2 of 18
X28HC64
Pin Descriptions
SYMBOL
A
0
-A
12
DESCRIPTION
Address Inputs. The Address inputs
select an 8-bit memory location
during a read or write operation.
Data Input/Output. Data is written
to or read from the X28HC64
through the I/O pins.
Write Enable. The Write Enable
input controls the writing of data to
the X28HC64.
Chip Enable. The Chip Enable input
must be LOW to enable all
read/write operations. When CE is
HIGH, power consumption is
reduced.
Output Enable. The Output Enable
input controls the data output
buffers and is used to initiate read
operations.
+5V
Ground
No Connect
Write
Write operations are initiated when both CE and WE are LOW and
OE is HIGH. The X28HC64 supports both a CE and WE controlled
write cycle. That is, the address is latched by the falling edge of
either CE or WE, whichever occurs last. Similarly, the data is
latched internally by the rising edge of either CE or WE, whichever
occurs first. A byte write operation, once initiated, will
automatically continue to completion, typically within 2ms.
I/O
0
-I/O
7
WE
Page Write Operation
The page write feature of the X28HC64 allows the entire memory
to be written in 0.25 seconds. Page write allows two to sixty-four
bytes of data to be consecutively written to the X28HC64 prior to
the commencement of the internal programming cycle. The host
can fetch data from another device within the system during a
page write operation (change the source address), but the page
address (A
6
through A
12
) for each subsequent valid write cycle to
the part during this operation must be the same as the initial page
address.
The page write mode can be initiated during any write operation.
Following the initial byte write cycle, the host can write an
additional one to sixty-three bytes in the same manner. Each
successive byte load cycle, started by the WE HIGH to LOW
transition, must begin within 100µs of the falling edge of the
preceding WE. If a subsequent WE HIGH to LOW transition is not
detected within 100µs, the internal automatic programming
cycle will commence. There is no page write window limitation.
Effectively the page write window is infinitely wide, so long as the
host continues to access the device within the byte load cycle
time of 100µs.
CE
OE
V
CC
V
SS
NC
Block Diagram
X BUFFERS
LATCHES AND
DECODER
A
0
–A
12
ADDRESS
INPUTS
Y BUFFERS
LATCHES
AND
DECODER
I/O BUFFERS
AND LATCHES
65,536-BIT
EEPROM
ARRAY
Write Operation Status Bits
The X28HC64 provides the user two write operation status bits.
These can be used to optimize a system write cycle time. The
status bits are mapped onto the I/O bus as shown in
Figure 2.
I/O
DP
TB
5
4
3
2
1
0
RESERVED
TOGGLE BIT
CE
OE
WE
V
CC
V
SS
CONTROL
LOGIC AND
TIMING
DATA POLLING
I/O
0
–I/O
7
DATA INPUTS/OUTPUTS
FIGURE 2. STATUS BIT ASSIGNMENT
FIGURE 1. BLOCK DIAGRAM
Device Operation
Read
Read operations are initiated by both OE and CE LOW. The read
operation is terminated by either CE or OE returning HIGH. This
two line control architecture eliminates bus contention in a
system environment. The data bus will be in a high impedance
state when either OE or CE is HIGH.
FN8109 Rev 4.00
June 27, 2016
Page 3 of 18
X28HC64
DATA Polling (I/O
7
)
The X28HC64 features DATA Polling as a method to indicate to
the host system that the byte write or page write cycle has
completed. DATA Polling allows a simple bit test operation to
determine the status of the X28HC64, eliminating additional
interrupt inputs or external hardware. During the internal
programming cycle, any attempt to read the last byte written will
LAST
WRITE
produce the complement of that data on I/O
7
(i.e., write data =
0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is
complete, I/O
7
will reflect true data.
DATA Polling can effectively reduce the time for writing to the
X28HC64. The timing diagram in
Figure 3
illustrates the
sequence of events on the bus. The software flow diagram in
Figure 4
illustrates one method of implementing the routine.
WE
CE
OE
V
IH
I/O
7
HIGH Z
V
OL
A
0
–A
12
V
OH
X28HC64
READY
An
An
An
An
An
An
An
FIGURE 3. DATA POLLING BUS SEQUENCE
WRITE DATA
WRITES
COMPLETE?
YES
SAVE LAST DATA
AND ADDRESS
NO
READ LAST
ADDRESS
IO
7
COMPARE?
YES
NO
READY
FIGURE 4. DATA POLLING SOFTWARE FLOW
FN8109 Rev 4.00
June 27, 2016
Page 4 of 18
X28HC64
Toggle Bit (I/O
6
)
The X28HC64 also provides another method for determining
when the internal write cycle is complete. During the internal
programming cycle I/O
6
will toggle from HIGH to LOW and LOW
to HIGH on subsequent attempts to read the device. When the
internal cycle is complete, the toggling will cease and the device
will be accessible for additional read or write operations.
The Toggle Bit can eliminate the chore of saving and fetching the
last address and data in order to implement DATA Polling. This
can be especially helpful in an array comprised of multiple
X28HC64 memories that is frequently updated. Toggle Bit Polling
can also provide a method for status checking in multiprocessor
applications. The timing diagram in
Figure 5
illustrates the
sequence of events on the bus. The software flow diagram in
Figure 6
illustrates a method for polling the Toggle Bit.
WE
LAST
WRITE
CE
OE
I/O
6
V
OH
*
V
OL
HIGH Z
*
X28HC64
READY
* BEGINNING AND ENDING STATE OF I/O
6
WILL VARY.
FIGURE 5. TOGGLE BIT BUS SEQUENCE
LAST WRITE
YES
LOAD ACCUM
FROM ADDR N
COMPARE
ACCUM WITH
ADDR N
COMPARE
OK?
YES
NO
READY
FIGURE 6. TOGGLE BIT SOFTWARE FLOW
FN8109 Rev 4.00
June 27, 2016
Page 5 of 18
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