March 1998
FDC633N
N-Channel Enhancement Mode Field Effect Transistor
General Description
This N-Channel enhancement mode power field effect
transistors is produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
tailored to minimize on-state resistance. These devices are
particularly suited for low voltage applications in notebook
computers, portable phones, PCMICA cards, and other
battery powered circuits where fast switching,low in-line
power loss and resistance to transients are needed in a very
small outline surface mount package.
Features
5.2 A, 30 V. R
DS(ON)
= 0.042
Ω
@ V
GS
= 4.5 V
R
DS(ON)
= 0.054
Ω
@ V
GS
= 2.5 V.
SuperSOT
TM
-6 package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
SOT-23
SuperSOT
TM
-6
SuperSOT
TM
-8
SO-8
SOT-223
SOIC-16
S
D
D
1
6
.63
3
2
5
G
SuperSOT
TM
pin
1
D
D
3
4
-6
Absolute Maximum Ratings
T
A
= 25°C unless otherwise noted
Symbol Parameter
V
DSS
V
GSS
I
D
P
D
Drain-Source Voltage
Gate-Source Voltage - Continuous
Drain Current - Continuous
- Pulsed
Maximum Power Dissipation
(Note 1a)
(Note 1b)
(Note 1a)
FDC633N
30
±8
5.2
16
1.6
0.8
-55 to 150
Units
V
V
A
W
T
J
,T
STG
R
θJA
R
θJC
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
78
30
°C/W
°C/W
© 1998 Fairchild Semiconductor Corporation
FDC633N Rev.C
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Zero Gate Voltage Drain Current
V
GS
= 0 V, I
D
= 250 µA
I
D
= 250 µA, Referenced to 25 C
V
DS
= 24 V, V
GS
= 0 V
T
J
= 55
o
C
I
GSSF
I
GSSR
V
GS(th)
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
V
GS
= 8 V, V
DS
= 0 V
V
GS
= -8 V, V
DS
= 0 V
V
DS
= V
GS
, I
D
= 250 µA
I
D
= 250 µA, Referenced to 25
o
C
V
GS
= 4.5 V, I
D
= 5.2 A
T
J
= 125 C
V
GS
= 2.5 V, I
D
= 4.5 A
I
D(on)
g
FS
C
iss
C
oss
C
rss
t
D(on)
t
r
t
D(off)
t
f
Q
g
Q
gs
Q
gd
I
S
V
SD
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
a. 78
o
C/W when mounted on a 1 in
2
pad of 2oz Cu on FR-4 board.
b. 156
o
C/W when mounted on a minimum pad of 2oz Cu on FR-4 board.
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
o
o
30
42
1
10
100
-100
V
mV/
o
C
µA
µA
nA
nA
∆
BV
DSS
/
∆
T
J
I
DSS
ON CHARACTERISTICS
(Note 2)
Gate Threshold Voltage
Gate Threshold VoltageTemp.Coefficient
Static Drain-Source On-Resistance
0.4
0.67
-2.4
0.033
0.051
0.043
1
V
mV/
o
C
∆
V
GS(th)
/
∆
T
J
R
DS(ON)
0.042
0.07
0.054
Ω
On-State Drain Current
Forward Transconductance
V
GS
= 4.5 V, V
DS
= 5 V
V
DS
= 10 V, I
D
= 5.2 A
V
DS
= 10 V, V
GS
= 0 V,
f = 1.0 MHz
11
15
A
S
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
538
226
51
pF
pF
pF
SWITCHING CHARACTERISTICS
(Note 2)
Turn - On Delay Time
Turn - On Rise Time
Turn - Off Delay Time
Turn - Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DS
= 10 V, I
D
= 5.2 A,
V
GS
= 4.5 V
V
DD
= 5 V, I
D
= 1 A,
V
GS
= 4.5 V, R
GEN
= 6
Ω
5
17
25
5.3
11
2
2.4
12
27
40
11
16
ns
ns
ns
ns
nC
nC
nC
DRAIN-SOURCE DIODE CHARACTERISTICS
Continuous Source Diode Current
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= 1.3 A
(Note 2)
1.3
0.7
o
A
V
1.2
1
T
J
= 125 C
0.57
FDC633N Rev.C
Typical Electrical Characteristics
20
I
D
, DRAIN-SOURCE CURRENT (A)
2
V
GS
= 4.5V
3.0
R
DS(ON)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
2.5
15
1.8
1.6
1.4
1.2
1
0.8
V
GS
= 2.0V
2.0
10
2.5
3.0
3.5
4.5
5
1.5
0
0
0.5
1
1.5
2
2.5
3
0
5
V
DS
, DRAIN-SOURCE VOLTAGE (V)
10
I
D
, DRAIN CURRENT (A)
15
20
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
R
DS(ON)
, ON-RESISTANCE (OHM)
1.6
DRAIN-SOURCE ON-RESISTANCE
0.15
I
D
= 5.2A
1.4
I
D
= 2.5A
0.12
R
DS(ON)
, NORMALIZED
V
GS
= 4.5V
0.09
1.2
0.06
T
A
= 125°C
1
0.03
0.8
T = 25°C
A
0
0.6
-50
1
2
V
GS
3
4
5
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
, GATE TO SOURCE VOLTAGE (V)
Figure 3. On-Resistance Variation
with Temperature.
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
V
DS
= 5V
I
D
, DRAIN CURRENT (A)
12
TJ = -55°C
25°C
125°C
I
S
, REVERSE DRAIN CURRENT (A)
15
15
V
GS
= 0V
T = 125°C
J
1
25°C
0.1
9
-55°C
0.01
6
3
0.001
0
0.0001
0
0.5
V
GS
1
1.5
2
2.5
0
0.2
0.4
0.6
0.8
1
1.2
, GATE TO SOURCE VOLTAGE (V)
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage
Variation with Source Current
and Temperature.
FDC633N Rev.C
Typical Electrical Characteristics
(continued)
5
V
GS
, GATE-SOURCE VOLTAGE (V)
1300
I
D
= 5.2A
4
V
DS
= 5V
10V
CAPACITANCE (pF)
600
300
15V
C
iss
3
Coss
100
50
2
1
f = 1 MHz
V
GS
= 0 V
0.3
1
3
C
rss
0
0
3
6
9
12
15
Q
g
, GATE CHARGE (nC)
20
0.1
10
30
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics.
Figure 8. Capacitance Characteristics.
40
20
10
I
D
, DRAIN CURRENT (A)
5
2
1
0.5
MIT
) LI
ON
S(
RD
5
100
1m
s
10m
s
us
POWER (W)
4
SINGLE PULSE
R
θ
JA
=See note 1b
T
A
= 25°C
3
10
0m
s
1s
2
0.1
0.05
V
GS
= 4.5V
SINGLE PULSE
R
θ
JA
= See Note 1b
T
A
= 25°C
A
0.2
0.5
1
2
DC
1
0.01
0.1
0
0.01
0.1
1
10
100
300
5
10
30
50
SINGLE PULSE TIME (SEC)
V
DS
, DRAIN-SOURCE VOLTAGE (V)
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum Power
Dissipation.
1
TRANSIENT THERMAL RESISTANCE
r(t), NORMALIZED EFFECTIVE
0.5
0.2
0.1
0.05
0.02
0.01
0.005
D = 0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
P(pk)
R
JA
(t) = r(t) * R
θ
JA
θ
R
= See Note 1b
θ
JA
t
1
t
2
T
J
- T
A
= P * R
θ
JA
(t)
Duty Cycle, D = t
1
/ t
2
0.00001
0.0001
0.001
0.01
0.1
t
1
, TIME (sec)
1
10
100
300
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in note 1b.
Transient thermal response will change depending on the circuit board design.
FDC633N Rev.C
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
DenseTrench™
DOME™
EcoSPARK™
E
2
CMOS
TM
EnSigna
TM
FACT™
FACT Quiet Series™
DISCLAIMER
FAST
®
FASTr™
FRFET™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
OPTOLOGIC™
OPTOPLANAR™
PACMAN™
POP™
Power247™
PowerTrench
®
QFET™
QS™
QT Optoelectronics™
Quiet Series™
SILENT SWITCHER
®
SMART START™
STAR*POWER™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
TruTranslation™
UHC™
UltraFET
®
VCX™
STAR*POWER is used under license
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
2. A critical component is any component of a life
systems which, (a) are intended for surgical implant into
support device or system whose failure to perform can
the body, or (b) support or sustain life, or (c) whose
be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance
support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Advance Information
Product Status
Formative or
In Design
Definition
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4
国产芯片交流
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
