Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
S70FL01GS
1 Gbit (128 Mbyte) 3.0V SPI Flash
Features
CMOS 3.0V Core
Serial Peripheral Interface (SPI) with Multi-I/O
– SPI Clock polarity and phase modes 0 and 3
– Double Data Rate (DDR) option
– Extended Addressing: 32-bit address
– Serial Command set and footprint compatible with
S25FL-A, S25FL-K, and S25FL-P SPI families
– Multi I/O Command set and footprint compatible with
S25FL-P SPI family
READ Commands
– Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad
DDR
– AutoBoot – power up or reset and execute a Normal or
Quad read command automatically at a preselected
address
– Common Flash Interface (CFI) data for configuration
information
Programming (1.5 Mbytes/s)
– 512-byte Page Programming buffer
– Quad-Input Page Programming (QPP) for slow clock
systems
Erase (0.5 Mbytes/s)
– Uniform 256-kbyte sectors
Cycling Endurance
– 100,000 Program-Erase Cycles, minimum
Data Retention
– 20 Year Data Retention, minimum
Security Features
One Time Program (OTP) array of 2048 bytes
Block Protection
– Status Register bits to control protection against program
or erase of a contiguous range of sectors.
– Hardware and software control options
– Advanced Sector Protection (ASP)
– Individual sector protection controlled by boot code or
password
Cypress
®
65 nm MirrorBit
®
Technology with Eclipse
Architecture
Core Supply Voltage: 2.7V to 3.6V
I/O Supply Voltage: 1.65V to 3.6V
Temperature Range / Grade:
– Industrial (40 °C to +85 °C)
– Industrial Plus (40 °C to +105 °C)
– Automotive, AEC-Q100 Grade 3 (40 °C to +85 °C)
– Automotive, AEC-Q100 Grade 2 (40 °C to +105 °C)
– Automotive, AEC-Q100 Grade 1 (40 °C to +125 °C)
Packages (all Pb-free)
– 16-lead SOIC (300 mils)
– BGA-24, 8
6 mm
– 5
5 ball (ZSA024) footprint
General Description
This document contains information for the S70FL01GS device, which is a dual die stack of two S25FL512S die. For detailed
specifications, refer to the discrete die datasheet provided in the
Affected Documents/Related Documents
table.
Affected Documents/Related Documents
Document Title
S25FL512S 512 Mbit (64 Mbyte) 3.0V SPI Flash Memory Datasheet
Publication Number
001-98284
Cypress Semiconductor Corporation
Document Number: 001-98295 Rev. *N
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 03, 2018
S70FL01GS
Contents
1.
2.
3.
4.
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.
6.
7.
8.
9.
Block Diagram..............................................................
3
Connection Diagrams..................................................
4
Input/Output Summary
................................................ 5
Device Operations
.......................................................
Programming .................................................................
Simultaneous Die Operation ..........................................
Sequential Reads...........................................................
Sector/Bulk Erase ..........................................................
Status Registers.............................................................
Configuration Register ...................................................
Bank Address Register ..................................................
Security and DDR Registers ..........................................
Block Protection .............................................................
6
6
6
6
6
6
6
6
6
6
10. SDR AC Characteristics
............................................. 10
10.1 DDR AC Characteristics ............................................... 11
10.2 Capacitance Characteristics ......................................... 11
11. Ordering Information
.................................................. 12
11.1 Valid Combinations — Standard................................... 13
11.2 Valid Combinations — Automotive Grade /
AEC-Q100 .................................................................... 13
12.
12.1
12.2
12.3
Other Resources
......................................................... 14
Cypress Flash Memory Roadmap ................................ 14
Links to Software .......................................................... 14
Links to Application Notes............................................. 14
Read Identification (RDID)...........................................
7
RESET#
......................................................................... 7
Versatile I/O Power Supply (V
IO
).................................
7
DC Characteristics.......................................................
8
AC Test Conditions......................................................
9
13. Physical Diagram
........................................................ 15
13.1 SOIC 16 Lead, 300-mil Body Width .............................. 15
13.2 24-Ball BGA 8 x 6 mm (ZSA024) .................................. 16
14. Revision History..........................................................
17
Sales, Solutions, and Legal Information .......................... 19
Worldwide Sales and Design Support ........................... 19
Products ........................................................................ 19
PSoC® Solutions .......................................................... 19
Cypress Developer Community ..................................... 19
Technical Support ......................................................... 19
Document Number: 001-98295 Rev. *N
Page 2 of 19
S70FL01GS
1. Block Diagram
SI/IO0
WP#/IO2
HOLD#/IO3
S I/IO 0
WP#/IO2
S O /IO 1
H O LD #/IO 3
SO/IO1
SCK
CS#1
SCK
CS#
FL512S
Flash
Memory
VSS
VSS
VCC
VCC
S I/IO 0
WP#/IO2
H O LD #/IO 3
S O /IO 1
SCK
CS#2
CS#
FL512S
Flash
Memory
VSS
VCC
Document Number: 001-98295 Rev. *N
Page 3 of 19
S70FL01GS
2.
Connection Diagrams
Figure 1. 16-Pin Plastic Small Outline Package (SO)
HOLD#/IO3
VCC
RESET#
DNU
DNU
CS2#
CS1#
SO/IO1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SCK
SI/IO0
VIO/RFU
NC
DNU
DNU
VSS
WP#/IO2
Figure 2. 24-Ball BGA, 5 x 5 Ball Footprint (ZSA024), Top View
1
A
DNU
B
DNU
C
DNU
D
DNU
E
DNU
DNU
DNU
VIO/RFU
DNU
SO/IO1
SI/IO0 HOLD#/IO3 DNU
CS1#
RFU
WP#/IO2
RFU
SCK
VSS
VCC
RFU
CS2#
RESET#
RFU
2
3
4
5
Note:
1. V
IO
is not supported in the S70FL01GS device and is RFU. Refer to
Section 7.
for more details.
Document Number: 001-98295 Rev. *N
Page 4 of 19
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