Pm25LV512A / 010A / 020 / 040
512 Kbit /1 Mbit / 2 Mbit / 4 Mbit 3.0 Volt-only,
Serial Flash Memory With 100 MHz SPI Bus Interface
FEATURES
Single Power Supply Operation
- Low voltage range: 2.7 V - 3.6 V
• Memory Organization
- Pm25LV512A: 64K x 8 (512 Kbit)
- Pm25LV010A: 128K x 8 (1 Mbit)
- Pm25LV020: 256K x 8 (2 Mbit)
- Pm25LV040: 512K x 8 (4 Mbit)
Cost Effective Sector/Block Architecture
-
512Kb : Uniform 4Kbyte sectors / Two uniform
32Kbyte blocks
-
1Mb : Uniform 4Kbyte sectors / Four uniform
32Kbyte blocks
- 2Mb : Uniform 4Kbyte sectors / Four uniform
64Kbyte blocks
- 4Mb : Uniform 4Kbyte sectors / Eight uniform
64Kbyte blocks
- Bottom sector is configurable as one 4Kbyte sector
or four 1Kbyte sectors (except Pm25LV512A)
Serial Peripheral Interface (SPI) Compatible
- Supports SPI Modes 0 (0,0) and 3 (1,1)
- Maximum 33 MHz clock rate for normal read
- Maximum 100 MHz clock rate for fast read
Page Program (up to 256 Bytes) Operation
- Typical 2 ms per page program
Sector, Block or Chip Erase Operation
- Typical 40 ms sector, block or chip erase
Software Write Protection
-
The Block Protect (BP2, BP1, BP0) bits allow partial
or entire memory to be configured as read-only
Hardware Write Protection
- Protect and unprotect the device from write operation
by Write Protect (WP#) Pin
Low Power Consumption
- Typical 10 mA active read current
- Typical 15 mA program/erase current
High Product Endurance
- Guarantee 200,000 program/erase cycles per single
sector
- Minimum 20 years data retention
Industrial Standard Pin-out and Package
- 8-pin 150mil SOIC
- 8-pin 208mil SOIC for Pm25LV040
- 8-contact WSON
GENERAL DESCRIPTION
The Pm25LV512A/010A/020/040 are 512Kbit/1 Mbit/2 Mbit/4 Mbit 3.0 Volt-only Serial Peripheral Interface (SPI)
Flash memories. The devices are designed to support 33 MHz fastest clock rate in the industry in normal read
mode, 100 MHz in fast read mode and the bottom 4 Kbyte sector into four smaller 1 Kbyte sectors features(except
Pm25LV512A). The devices use a single low voltage, ranging from 2.7 Volt to 3.6 Volt, power supply to perform
read, erase and program operations. The devices can be programmed in standard EPROM programmers as well.
The Pm25LV512A/010A is backward compatible to their predecessors Pm25LV512/010.
The Pm25LV512A/010A/020/040 are accessed through a 4-wire SPI Interface consists of Serial Data Input (Sl),
Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. The devices support page program
mode, 1 to 256 bytes data can be programmed into the memory in one program operation. The memory of
Pm25LV512A/010A is divided into uniform 4 Kbyte sectors or uniform 32 Kbyte blocks (sector group - consists of
eight adjacent sectors) for data or code storage. The memory of Pm25LV020/040 are divided into uniform 4 Kbyte
sectors or uniform 64 Kbyte blocks (sector group - consists of sixteen adjacent sectors). The devices have an
innovative feature to configure the bottom 4 Kbyte sector into four smaller 1 Kbyte sectors for eliminating additional
serial EEPROM needed for storing data. This is a further cost reduction for overall system.
The Pm25LV512A/010A/020/040 are manufactured on pFLASH™’s advanced nonvolatile technology. The devices
are offered in 8-pin SOIC and 8-contact WSON packages with operation frequency up to 100 MHz in fast read and
33 MHz in normal read mode.
Chingis Technology Corporation
1
Issue Date: June, 2006, Rev: 2.9
Pm25LV512A/010A/020/040
CONNECTION DIAGRAMS
CE#
SO
WP#
GND
1
2
3
4
8
7
6
5
Vcc
HOLD#
SCK
SI
CE#
SO
WP#
GND
1
2
3
4
8
7
6
5
Vcc
HOLD#
SCK
SI
8-Pin SOIC
8-Contact WSON
PIN DESCRIPTIONS
SYMBOL
TYPE
DESCRIPTION
Chip Enable: CE# goes low activates the devices internal circuitries for
device operation. CE# goes high deselects the devices and switches into
standby mode to reduce the power consumption. When the devices are not
selected, data will not be accepted via the serial input pin (Sl), and the
serial output pin (SO) will remain in a high impedance state.
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Device Power Supply
Write Protect: A hardware program/erase protection for all or partial of
memory array. When the WP# pin is pulled to low, whole or partial of
memory array is write protected depends on the setting of BP2, BP1 and
BP0 bits in the Status Register. When the WP# is pulled high, the devices
are not write protected.
Hold: Pause serial communication with the master device without resetting
the serial sequence.
CE#
INPUT
SCK
SI
SO
GND
Vcc
INPUT
INPUT
OUTPUT
WP#
INPUT
HOLD#
INPUT
Chingis Technology Corporation
2
Issue Date: June, 2006, Rev: 2.9
Pm25LV512A/010A/020/040
SPI MODES DESCRIPTION
Multiple Pm25LV512A/010A/020/040 devices can be se-
rially connected onto the SPI serial bus controlled by a
SPI Master i.e. microcontroller as shown in Figure 1.
The devices support either of the two SPI modes:
Mode 0 (0, 0)
Mode 3 (1, 1)
The difference between these two modes is the clock
polarity when the SPI master is in Stand-by mode: the
serial clock remains at “0” (SCK = 0) for Mode 0 and the
clock remains at “1” (SCK = 1) for Mode 1. Please refer
to Figure 2. For both modes, the input data is latched on
the rising edge of Serial Clock (SCK), and the output
data is available from the falling edge of SCK.
Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices)
SDO
SPI Interface with
(0, 0) or (1, 1)
SDI
SCK
SCK
SPI Master
(i.e. Microcontroller)
SO
SI
SCK SO
SI
SCK
SO
SI
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
CS3
CS2 CS1
CE#
WP# HOLD# CE#
WP# HOLD# CE#
WP# HOLD#
Note: 1. The Write Protect (WP#) and Hold (HOLD#) si gnals should be driven, High or Low as appropriate.
Figure 2. SPI Modes Supported
Mode 0 (0, 0)
SCK
Mode 3 (1, 1)
SCK
SI
MSB
SO
MSB
Chingis Technology Corporation
5
Issue Date: June, 2006, Rev: 2.9
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