0.13µm Process
ADVANCE
‡
36Mb: 2 MEG x 18, 1 MEG x 32/36
PIPELINED, SCD SYNCBURST SRAM
36Mb
SRAM
Features
SYNCBURST
™
MT58L2MY18P, MT58V2MV18P,
MT58L1MY32P, MT58V1MV32P,
MT58L1MY36P, MT58V1MV36P
3.3V V
DD
, 3.3V or 2.5V I/O; 2.5V V
DD
, 2.5V I/O
• Fast clock and OE# access times
• Single 3.3V ±5 percent or 2.5V ±5 percent power supply
• Separate 3.3V ±5 percent or 2.5V ±5 percent isolated
output buffer supply (V
DD
Q)
• SNOOZE MODE for reduced-power standby
• Single-cycle deselect (Pentium® BSRAM-compatible)
• Common data inputs and data outputs
• Individual BYTE WRITE control and GLOBAL WRITE
• Three chip enables for simple depth expansion and
address pipelining
• Clock-controlled and registered addresses, data
I/Os, and control signals
• Internally self-timed WRITE cycle
• Automatic power-down
• Burst control (interleaved or linear burst)
• Low capacitive bus loading
Figure 1: 100-Pin TQFP
JEDEC-Standard MS-026 BHA (LQFP)
Figure 2: 165-Ball FBGA
JEDEC-Standard MO-216 (Var. CAB-1)
Options
• Timing (Access/Cycle/MHz)
3.1ns/5ns/200 MHz
3.5ns/6ns/166 MHz
4.2ns/7.5ns/133 MHz
5ns/10ns/100 MHz
• Configurations
3.3V V
DD
, 3.3V or 2.5V I/O
2 Meg x 18
1 Meg x 32
1 Meg x 36
2.5V V
DD
, 2.5V I/O
2 Meg x 18
1 Meg x 32
1 Meg x 36
• Packages
100-pin, 16mm x 22.1mm TQFP
165-ball, 13mm x 15mm FBGA
TQFP
Marking
-5
-6
-7.5
-10
MT58L2MY18P
MT58L1MY32P
MT58L1MY36P
MT58V2MV18P
MT58V1MV32P
MT58V1MV36P
T
F
1
Part Number Example:
MT58L1MY36PT-10
General Description
The Micron® SyncBurst™ SRAM family employs
high-speed, low-power CMOS designs that are fabri-
cated using an advanced CMOS process.
Micron’s 36Mb SyncBurst SRAMs integrate a 2 Meg x
18, 1 Meg x 32, or 1 Meg x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single-clock
input (CLK). The synchronous inputs include all
addresses, all data inputs, active LOW chip enable
(CE#), two additional chip enables for easy depth
1
• Operating Temperature Range
Commercial (0ºC
£
T
A
£
+70ºC)
Industrial (-40ºC
£
T
A
£
+85ºC)
NOTE:
None
IT
2
1. A Part Marking Guide for the FBGA devices can be found on
Micron’s Web site—http://www.micron.com/numberguide.
2. Contact factory for availability of Industrial Temperature devices.
36Mb: 2 Meg x 18, 1 Meg x 32/36, Pipelined, SCD SyncBurst SRAM
MT58L2MY18P1_16_B.fm - Rev. B, Pub 1/03
©2003, Micron Technology Inc.
‡
PRODUCTS
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
0.13µm Process
ADVANCE
36Mb: 2 MEG x 18, 1 MEG x 32/36
PIPELINED, SCD SYNCBURST SRAM
expansion (CE2, CE2#), burst control inputs (ADSC#,
ADSP#, ADV#), byte write enables (BWx#), and global
write (GW#).
Asynchronous inputs include the output enable
(OE#), clock (CLK) and snooze enable (ZZ). There is
also a burst mode input (MODE) that selects between
interleaved and linear burst modes. The data-out (Q),
enabled by OE#, is also asynchronous. WRITE cycles
can be from one to two bytes wide (x18) or from one to
four bytes wide (x32/x36), as controlled by the write
control inputs.
Burst operation can be initiated with either address
status processor (ADSP#) or address status controller
(ADSC#) inputs. Subsequent burst addresses can be
internally generated as controlled by the burst
advance input (ADV#).
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During WRITE cycles on the x18 device,
BWa# controls DQa pins/balls and DQPa; BWb# con-
trols DQb pins/balls and DQPb. During WRITE cycles
on the x32 and x36 devices, BWa# controls DQa pins/
balls and DQPa; BWb# controls DQb pins/balls and
DQPb; BWc# controls DQc pins/balls and DQPc; BWd#
controls DQd pins/balls and DQPd. GW# LOW causes
all bytes to be written. Parity bits are only available on
the x18 and x36 versions.
This device incorporates a single-cycle deselect fea-
ture during READ cycles. If the device is immediately
deselected after a READ cycle, the output bus goes to a
High-Z state
t
KQHZ nanoseconds after the rising edge
of clock.
Micron’s 36Mb SyncBurst SRAMs operate from a
3.3V or 2.5V V
DD
power supply, and all inputs and out-
puts are LVTTL-compatible. Users can use either a 3.3V
or 2.5V I/O, depending on the V
DD
voltage. The device
is ideally suited for Pentium and PowerPC pipelined
systems and systems that benefit from a very wide,
high-speed data bus. The device is also ideal in generic
16-, 18-, 32-,36-, 64-, and 72-bit-wide applications.
Please refer to Micron’s Web site (www.micron.com/
sramds)
for the latest data sheet.
DUAL VOLTAGE I/O
The 3.3V V
DD
device is tested for 3.3V and 2.5V I/O
function. The 2.5V V
DD
device is tested for only 2.5V
I/O function.
36Mb: 2 Meg x 18, 1 Meg x 32/36, Pipelined, SCD SyncBurst SRAM
MT58L2MY18P1_16_B.fm - Rev. B, Pub 1/03
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology Inc.
0.13µm Process
ADVANCE
36Mb: 2 MEG x 18, 1 MEG x 32/36
PIPELINED, SCD SYNCBURST SRAM
Figure 3: Functional Block Diagram
2 Meg x 18
21
SA0, SA1, SAs
MODE
ADV#
CLK
ADDRESS
REGISTER
21
19
21
2
SA0-SA1
SA1'
BINARY Q1
COUNTER AND
LOGIC
CLR
Q0
SA0'
ADSC#
ADSP#
BYTE “b”
WRITE REGISTER
9
BYTE “b”
WRITE DRIVER
9
2 Meg x 9 x 2
MEMORY
ARRAY
9
18
SENSE
AMPS
18
BWb#
OUTPUT
REGISTERS
18
OUTPUT
BUFFERS
18
BWa#
BWE#
GW#
CE#
CE2
CE2#
OE#
BYTE “a”
WRITE REGISTER
9
BYTE “a”
WRITE DRIVER
E
DQs
DQPa
DQPb
ENABLE
REGISTER
18
PIPELINED
ENABLE
2
INPUT
REGISTERS
Figure 4: Functional Block Diagram
1 Meg x 32/36
20
SA0, SA1, SAs
ADDRESS
REGISTER
20
18
SA0-SA1
20
MODE
ADV#
CLK
Q1
SA1'
BINARY
COUNTER
SA0'
CLR
Q0
ADSC#
ADSP#
BWd#
BYTE “d”
WRITE REGISTER
BYTE “c”
WRITE REGISTER
9
BYTE
“d”
WRITE DRIVER
BYTE
“c”
WRITE DRIVER
BYTE
“b”
WRITE DRIVER
BYTE
“a”
WRITE DRIVER
9
BWc#
9
9
1 Meg x 8 x 4
(x32)
1 Meg x 9 x 4
(x36)
36
SENSE
AMPS
36
OUTPUT
REGISTERS
36
BWb#
BYTE “b”
WRITE REGISTER
9
9
MEMORY
ARRAY
OUTPUT
BUFFERS
E
36
DQs
DQPa
DQPb
DQPc
DQPd
BWa#
BWE#
GW#
CE#
CE2
CE2#
OE#
BYTE “a”
WRITE REGISTER
9
9
ENABLE
REGISTER
36
PIPELINED
ENABLE
4
INPUT
REGISTERS
NOTE:
Functional block diagrams illustrate simplified device operation. See truth tables, pin/ball descriptions, and tim-
ing diagrams for detailed information.
36Mb: 2 Meg x 18, 1 Meg x 32/36, Pipelined, SCD SyncBurst SRAM
MT58L2MY18P1_16_B.fm - Rev. B, Pub 1/03
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology Inc.
0.13µm Process
ADVANCE
36Mb: 2 MEG x 18, 1 MEG x 32/36
PIPELINED, SCD SYNCBURST SRAM
Figure 5: Pin layout (Top View)
100-Pin TQFP
SA
NC
NC
V
DD
Q
V
SS
NC
DQPa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
NC
NC
V
SS
V
DD
Q
NC
NC
NC
SA
SA
ADV#
ADSP#
ADSC#
OE# (G#)
BWE#
GW#
CLK
V
SS
V
DD
CE2#
BWa#
BWb#
NC
NC
CE2
CE#
SA
SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
49
82
48
83
47
84
46
85
45
86
44
87
43
88
42
89
41
90
40
91
39
92
38
93
37
94
36
95
35
96
34
97
33
98
32
99
31
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
x18
SA
SA
SA
SA
SA
SA
SA
SA
SA
V
DD
V
SS
SA
DNU2
SA0
SA1
SA
SA
SA
SA
MODE
(LBO#)
SA
SA
ADV#
ADSP#
ADSC#
OE# (G#)
BWE#
GW#
CLK
V
SS
V
DD
CE2#
BWa#
BWb#
BWc#
BWd#
CE2
CE#
SA
SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
49
82
48
83
47
84
46
85
45
86
44
87
43
88
42
89
41
90
40
91
39
92
38
93
37
94
36
95
35
96
34
97
33
98
32
99
31
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NF/DQPb
1
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQb
DQb
V
SS
V
DD
Q
DQb
DQb
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
NF/DQPa
1
NC
NC
NC
V
DD
Q
V
SS
NC
NC
DQb
DQb
V
SS
V
DD
Q
DQb
DQb
NC
V
DD
NC
V
SS
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQPb
NC
V
SS
V
DD
Q
NC
NC
NC
x32/x36
SA
SA
SA
SA
SA
SA
SA
SA
SA
V
DD
V
SS
SA
DNU2
SA0
SA1
SA
SA
SA
SA
MODE
(LBO#)
NOTE:
1. No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version.
2. Pin 38 is reserved for 72Mb address expansion.
.
36Mb: 2 Meg x 18, 1 Meg x 32/36, Pipelined, SCD SyncBurst SRAM
MT58L2MY18P1_16_B.fm - Rev. B, Pub 1/03
NF/DQPc
1
DQc
DQc
V
DD
Q
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DD
Q
DQc
DQc
NC
V
DD
NC
V
SS
DQd
DQd
V
DD
Q
V
SS
DQd
DQd
DQd
DQd
V
SS
V
DD
Q
DQd
DQd
NF/DQPd
1
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology Inc.
0.13µm Process
ADVANCE
36Mb: 2 MEG x 18, 1 MEG x 32/36
PIPELINED, SCD SYNCBURST SRAM
Table 1:
SYMBOL
ADV#
TQFP Pin Descriptions
TYPE
Input
DESCRIPTION
Synchronous Address Advance: This active LOW input is used to advance the internal burst
counter, controlling burst access after the external address is loaded. A HIGH on this pin
effectively causes wait states to be generated (no address advance). To ensure use of correct
address during a WRITE cycle, ADV# must be HIGH at the rising edge of the first clock after an
ADSP# cycle is initiated.
Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst,
causing a new external address to be registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but dependent upon CE#, CE2, and CE2#.
ADSP# is ignored if CE# is HIGH. Power-down state is entered if CE2 is LOW or CE2# is HIGH.
Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst,
causing a new external address to be registered. A READ or WRITE is performed using the
new address if CE# is LOW. ADSC# is also used to place the chip into power-down state when
CE# is HIGH.
Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be
written and must meet the setup and hold times around the rising edge of CLK. A byte write
enable is LOW for a WRITE cycle and HIGH for a READ cycle. For the x18 version, BWa#
controls DQa pins and DQPa; BWb# controls DQb pins and DQPb. For the x32 and x36
versions, BWa# controls DQa pins and DQPa; BWb# controls DQb pins and DQPb; BWc#
controls DQc pins and DQPc; BWd# controls DQd pins and DQPd. Parity is only available on
the x18 and x36 versions.
Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet the
setup and hold times around the rising edge of CLK.
Synchronous Chip Enable: This active LOW input is used to enable the device and conditions
the internal use of ADSP#. CE# is sampled only when a new external address is loaded.
Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled
only when a new external address is loaded.
Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled
only when a new external address is loaded.
Clock: This signal registers the address, data, chip enable, byte write enables, and burst
control inputs on its rising edge. All synchronous inputs must meet setup and hold times
around the clock’s rising edge.
Global Write: This active LOW input allows a full 18-, 32-, or 36-bit WRITE to occur
independent of the BWE# and BWx# lines and must meet the setup and hold times around
the rising edge of CLK.
Mode: This input selects the burst sequence. A LOW on this pin selects “linear burst.” NC or
HIGH on this pin selects “interleaved burst.” Do not alter input state while device is
operating. LBO# is the JEDEC-standard term for MODE.
Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. G# is
the JEDEC-standard term for OE#.
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold
times around the rising edge of CLK.
Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power
standby mode in which all data in the memory array is retained. When ZZ is active, all other
inputs are ignored. This pin has an internal pull-down and can be left unconnected.
SRAM Data I/Os: For the x18 version, byte “a” is associated with DQa pins; byte “b” is
associated with DQb pins. For the x32 and x36 versions, byte “a” is associated with DQa pins;
byte “b” is associated with DQb pins; byte “c” is associated with DQc pins; byte “d” is
associated with DQd pins. Input data must meet setup and hold times around the rising edge
of CLK.
ADSP#
Input
ADSC#
Input
BWa#
BWb#
BWc#
BWd#
Input
BWE#
CE#
CE2#
CE2
CLK
Input
Input
Input
Input
Input
GW#
Input
MODE
(LBO#)
OE# (G#)
SA0
SA1
SA
ZZ
Input
Input
Input
Input
DQa
DQb
DQc
DQd
Input/
Output
36Mb: 2 Meg x 18, 1 Meg x 32/36, Pipelined, SCD SyncBurst SRAM
MT58L2MY18P1_16_B.fm - Rev. B, Pub 1/03
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology Inc.
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