GTLP18T612 18-Bit LVTTL/GTLP Universal Bus Transceiver
May 1999
Revised July 2002
GTLP18T612
18-Bit LVTTL/GTLP Universal Bus Transceiver
General Description
The GTLP18T612 is an 18-bit universal bus transceiver
which provides LVTTL to GTLP signal level translation. It
allows for transparent, latched and clocked modes of data
transfer. The device provides a high speed interface for
cards operating at LVTTL logic levels and a backplane
operating at GTLP logic levels. High speed backplane
operation is a direct result of GTLP’s reduced output swing
(
<
1V), reduced input threshold levels and output edge rate
control. The edge rate control minimizes bus settling time.
GTLP is a Fairchild Semiconductor derivative of the Gun-
ning Transistor logic (GTL) JEDEC standard JESD8-3.
Fairchild’s GTLP has internal edge-rate control and is Pro-
cess, Voltage, and Temperature (PVT) compensated. Its
function is similar to BTL or GTL but with different output
levels and receiver thresholds. GTLP output LOW level is
less than 0.5V, the output HIGH is 1.5V and the receiver
threshold is 1.0V.
Features
s
Bidirectional interface between GTLP and LVTTL logic
levels
s
Designed with edge rate control circuitry to reduce out-
put noise on the GTLP port
s
V
REF
pin provides external supply reference voltage for
receiver threshold adjustibility
s
Special PVT compensation circuitry to provide consis-
tent performance over variations of process, supply volt-
age and temperature
s
TTL compatible driver and control inputs
s
Designed using Fairchild advanced BiCMOS technology
s
Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs
s
Power up/down and power off high impedance for live
insertion
s
Open drain on GTLP to support wired-or connection
s
Flow through pinout optimizes PCB layout
s
D-type flip-flop, latch and transparent data paths
s
A Port source/sink
−
24mA/
+
24mA
s
B Port sink
+
50mA
s
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Ordering Code:
Order Number
GTLP18T612G
(Note 1)(Note 2)
GTLP18T612MEA
(Note 2)
GTLP18T612MTD
(Note 2)
Package Number
BGA54A
MS56A
MTD56
Package Description
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1:
Ordering code “G” indicates Trays.
Note 2:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
© 2002 Fairchild Semiconductor Corporation
DS500169
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GTLP18T612
Connection Diagrams
Pin Assignments for SSOP and TSSOP
Pin Descriptions
Pin Names
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
V
REF
CLKAB
CLKBA
A1–A18
B1–B18
Description
A-to-B Output Enable
(Active LOW) (LVTTL Level)
B-to-A Output Enable
(Active LOW) (LVTTL Level)
A-to-B Clock/LE Enable
(Active LOW) (LVTTL Level)
B-to-A Clock/LE Enable
(Active LOW) (LVTTL Level)
A-to-B Latch Enable
(Transparent HIGH) (LVTTL Level)
B-to-A Latch Enable
(Transparent HIGH) (LVTTL Level)
GTLP Input Threshold
Reference Voltage
A-to-B Clock (LVTTL Level)
B-to-A Clock (LVTTL Level)
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B-to-A Data Inputs or
A-to-B Open Drain Outputs
FBGA Pin Assignments
1
A
B
C
D
E
F
Pin Assignments for FBGA
G
H
J
A
2
A
4
A
6
A
8
A
10
A
12
A
14
A
16
A
18
2
A
1
A
3
A
5
A
7
A
9
A
11
A
13
A
15
A
17
3
LEAB
V
CC
GND
GND
GND
V
CC
4
CEAB
V
CC
GND
GND
GND
V
REF
5
B
2
B
4
B
6
B
8
B
10
B
12
B
14
B
16
B
18
6
B
1
B
3
B
5
B
7
B
9
B
11
B
13
B
15
B
17
OEAB CLKAB
OEBA CEBA
LEBA CLKBA
(Top Thru View)
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2
GTLP18T612
Functional Description
The GTLP18T612 is an 18 bit registered transceiver con-
taining D-type flip-flop, latch and transparent modes of
operation for the data path. Data flow in each direction is
controlled by the clock enables (CEAB and CEBA), latch
enables (LEAB and LEBA), clock (CLKAB and CLKBA)
and output enables (OEAB and OEBA). The clock enables
(CEAB and CEBA) and the output enables (OEAB and
OEBA) control the 18 bits of data for the A-to-B and B-to-A
directions respectively.
For A-to-B data flow, when CEAB is LOW, the device oper-
ates on the LOW-to-HIGH transition of CLKAB for the flip-
flop and on the HIGH-to-LOW transition of LEAB for the
latch path. That is, if CEAB is LOW and LEAB is LOW the
A data is latched regardless as to the state of CLKAB
(HIGH or LOW) and if LEAB is HIGH the device is in trans-
parent mode. When OEAB is LOW the outputs are active.
When OEAB is HIGH the outputs are HIGH impedance.
The data flow of B-to-A is similar except that CEBA, OEBA,
LEBA, and CLKBA are used.
Truth Table
(Note 3)
Inputs
CEAB OEAB LEAB CLKAB A
X
L
L
X
X
L
L
H
H
L
L
L
L
L
L
L
X
L
L
H
H
L
L
L
X
H
L
X
X
X
Output
B
Z
Latched
Storage
of A Data
Transparent
Clocked
Storage
of A Data
X
X B
0
(Note 5) Clock Inhibit
Note 3:
A-to-B data flow is shown. B-to-A data flow is similar but uses
OEBA, LEBA, CLKBA, and CEBA.
Note 4:
Output level before the indicated steady state input conditions were
established, provided that CLKAB was HIGH before LEAB went LOW.
Note 5:
Output level before the indicated steady-state input conditions
were established.
Mode
X B
0
(Note 4)
X B
0
(Note 5)
L
H
L
H
L
H
L
H
↑
↑
Logic Diagram
3
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GTLP18T612
Absolute Maximum Ratings
(Note 6)
Supply Voltage (V
CC
)
DC Input Voltage (V
I
)
DC Output Voltage (V
O
)
Outputs 3-STATE
Outputs Active (Note 7)
DC Output Sink Current into
A Port I
OL
DC Output Source Current from
A Port I
OH
DC Output Sink Current into
B Port in the LOW State, I
OL
DC Input Diode Current (I
IK
)
V
I
<
0V
DC Output Diode Current (I
OK
)
V
O
<
0V
V
O
>
V
CC
ESD Performance
Storage Temperature (T
STG
)
100 mA
48 mA
−
0.5V to
+
4.6V
−
0.5V to
+
4.6V
−
0.5V to
+
4.6V
−
0.5V to V
CC
+
0.5V
Recommended Operating
Conditions
(Note 8)
Supply Voltage V
CC
/V
CCQ
Bus Termination Voltage (V
TT
)
GTLP
V
REF
Input Voltage (V
I
)
on A Port and Control Pins
on B Port
HIGH Level Output Current (I
OH
)
A Port
LOW Level Output Current (I
OL
)
A Port
0.0V to 3.45V
0.0V to 3.45V
1.47V to 1.53V
0.98V to 1.02V
3.15V to 3.45V
−
48 mA
−
24 mA
+
24 mA
+
50 mA
−
40
°
C to
+
85
°
C
−
50 mA
−
50 mA
+
50 mA
>
2000V
−
65
°
C to
+
150
°
C
B Port
Operating Temperature (T
A
)
Note 6:
Absolute Maximum continuous ratings are those values beyond
which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability.
Functional operation under absolute maximum rated conditions in not
implied.
Note 7:
I
O
Absolute Maximum Rating must be observed.
Note 8:
Unused inputs must be held HIGH or LOW.
DC Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range, V
REF
=
1.0V (unless otherwise noted).
Symbol
V
IH
V
IL
V
REF
V
IK
V
OH
A Port
B Port
Others
B Port
Others
GTLP (Note 10)
GTL
V
CC
=
3.15V
V
CC
=
3.15V
V
OL
A Port
B Port
I
I
Control Pins
A Port
B Port
I
OFF
I
I(hold)
I
OZH
I
OZL
I
CC
(V
CC
/V
CCQ
)
I
I
= −18
mA
V
CC
–0.2
2.4
2.0
0.2
0.5
0.40
0.55
±5
−10
10
5
−5
30
75
−75
10
5
−10
−5
30
30
30
40
40
45
mA
V
V
µA
µA
µA
µA
µA
µA
µA
V
I
OH
= −8
mA
I
OH
= -24mA
V
CC
, V
CCQ
=
Min to Max (Note 11) I
OL
=
100
µA
V
CC
=
3.15V
V
CC
=
3.15V
V
CC
=
Min to Max (Note 11)
V
CC
=
3.45V
V
CC
=
3.45V
I
OL
=
24mA
I
OL
=
40 mA
I
OL
=
50 mA
V
I
=
3.45V or 0V
V
I
=
0V
V
I
=
3.45
V
I
=
V
CC
V
I
=
0
A Port and Control Pins V
CC
=
0
A Port
A Port
B Port
A Port
B Port
A or B Ports
V
CC
=
3.45V
I
O
=
0
V
I
=
V
CC
or GND
V
CC
=
3.45V
V
CC
=
3.15V
V
CC
=
3.45V
V
I
or V
O
=
0 to 3.45V
V
I
=
0.8V
V
I
=
2.0V
V
O
=
3.45
V
O
=
1.5V
V
O
=
0V
V
O
=
0.55V
Outputs HIGH
Outputs LOW
Outputs Disabled
V
CC
, V
CCQ
=
Min to Max (Note 11) I
OH
= −100 µA
1.0
0.8
−1.2
Test Conditions
Min
V
REF
+0.05
2.0
0.0
V
REF
−
0.05
0.8
Typ
(Note 9)
V
TT
V
V
V
V
Max
Units
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4
GTLP18T612
DC Electrical Characteristics
Symbol
∆I
CC
(Note 12)
C
i
A Port and
Control Pins
Control Pins
A Port
B Port
V
CC
=
3.45V,
(Continued)
Min
Typ
(Note 9)
0
6
7.5
9.0
pF
2
mA
Max
Units
Test Conditions
One Input at 2.7V
V
I
=
V
CC
or 0
V
I
=
V
CC
or 0
V
I
=
V
CC
or 0
A or Control Inputs at V
CC
or GND
Note 9:
All typical values are at V
CC
=
3.3V, V
CCQ
=
3.3V, and T
A
=
25°C.
Note 10:
GTLP V
REF
and V
TT
are specified to 2% tolerance since signal integrity and noise margin can be significantly degraded if these supplies are noisy.
In addition, V
TT
and Rterm can be adjusted beyond the recommended operating conditions to accommodate backplane impedances other than 50Ω, but
must remain within the boundaries of the DC Absolute Maximum ratings. Similarly V
REF
can be adjusted to optimize noise margin.
Note 11:
For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
Note 12:
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
or GND.
AC Operating Requirements
Over recommended ranges of supply voltage and operating free-air temperature, V
REF
=
1.0V (unless otherwise noted).
Symbol
f
MAX
t
WIDTH
t
SU
Maximum Clock Frequency
Pulse Duration
Setup Time
LEAB or LEBA HIGH
CLKAB or CLKBA HIGH or LOW
A before CLKAB↑
B before CLKBA↑
A before LEAB
B before LEBA
CEAB before CLKAB↑
CEBA before CLKBA↑
t
HOLD
Hold Time
A after CLKAB↑
B after CLKBA↑
A after LEAB
B after LEBA
CEAB after CLKAB↑
CEBA after CLKBA↑
Test Conditions
Min
175
3.0
3.0
1.1
3.0
1.1
2.7
1.2
1.4
0.0
0.0
0.8
0.0
1.0
1.9
ns
ns
Max
Unit
MHz
ns
5
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