IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B,
IS61VPS/VVPS51218B, IS61VPS/VVPS25636B
256K x 36, 256K x 32, 512K x 18
9 Mb SYNCHRONOUS PIPELINED,
SINgLE CYCLE DESELECT STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth ex-
pansion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• JTAG Boundary Scan for BGA package
• Power Supply
LPS: V
dd
3.3V (+ 5%),
V
ddq
3.3V/2.5V (+ 5%)
VPS: V
dd
2.5V (+ 5%),
V
ddq
2.5V (+ 5%)
VVPS: V
dd
1.8V (+ 5%),
V
ddq
1.8V (+ 5%)
• JEDEC 100-Pin QFP, 119-ball BGA, and 165-
ball BGA packages
• Lead-free available
MAY 2017
DESCRIPTION
The 9Mb product family features high-speed, low-power
synchronous static RAMs designed to provide burstable,
high-performance memory for communication and net-
working applications. The IS61LPS/VPS25636B and
IS64LPS25636B are organized as 262,144 words by
36 bits. The IS61LPS25632B is organized as 262,144
words by 32 bits. The IS61LPS/VPS51218B is organized
as 524,288 words by 18 bits. Fabricated with
ISSI
's ad-
vanced CMOS technology, the device integrates a 2-bit
burst counter, high-speed SRAM core, and high-drive
capability outputs into a single monolithic circuit. All
synchronous inputs pass through registers controlled by
a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be
one to four bytes wide as controlled by the write control
inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte
write enable (BWE) input combined with one or more
individual byte write signals (BWx). In addition, Global
Write (GW) is available for writing all bytes at one time,
regardless of the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be gener-
ated internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence or-
der, Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH
or left floating.
250
2.6
4
250
200
3.1
5
200
166
3.8
6
166
Units
ns
ns
MHz
FAST ACCESS TIME
Symbol
t
kq
t
kc
Parameter
Clock Access Time
Cycle Time
Frequency
Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. B3
05/26/2017
1
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
