INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT299
8-bit universal shift register; 3-state
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
8-bit universal shift register; 3-state
FEATURES
•
Multiplexed inputs/outputs provide improved bit density
•
Four operating modes:
– shift left
– shift right
– hold (store)
– load data
•
Operates with output enable or at high-impedance
OFF-state (Z)
•
3-state outputs drive bus lines directly
•
Can be cascaded for n-bits word length
•
Output capability: bus driver (parallel I/Os),
standard (serial outputs)
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT299 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT299
The 74HC/HCT299 contain eight edge-triggered D-type
flip-flops and the interstage logic necessary to perform
synchronous shift-right, shift-left, parallel load and hold
operations. The type of operation is determined by the
mode select inputs (S
0
and S
1
), as shown in the mode
select table.
All flip-flop outputs have 3-state buffers to separate these
outputs (I/O
0
to I/O
7
) such, that they can serve as data
inputs in the parallel load mode. The serial outputs (Q
0
and
Q
7
) are used for expansion in serial shifting of longer
words.
A LOW signal on the asynchronous master reset input
(MR) overrides the S
n
and clock (CP) inputs and resets the
flip-flops. All other state changes are initiated by the rising
edge of the clock pulse. Inputs can change when the clock
is either state, provided that the recommended set-up and
hold times, relative to the rising edge of CP, are observed.
A HIGH signal on the 3-state output enable inputs (OE
1
or
OE
2
) disables the 3-state buffers and the I/O
n
outputs are
set to the high-impedance OFF-state. In this condition, the
shift, hold, load and reset operations can still occur. The
3-state buffers are also disabled by HIGH signals on both
S
0
and S
1
, when in preparation for a parallel load
operation.
TYPICAL
SYMBOL
t
PHL/
t
PLH
PARAMETER
propagation delay
CP to Q
0
, Q
7
CP to I/O
n
t
PHL
f
max
C
I
C
I/O
C
PD
Notes
1. C
PD
is used to determine the dynamic power
dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC
×
f
o
) = sum of outputs
2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
20
20
20
50
3.5
10
notes 1 and 2
120
19
19
23
46
3.5
10
125
HCT
UNIT
ns
ns
ns
MHz
pF
pF
pF
MR to Q
0
, Q
7
or I/O
n
maximum clock frequency
input capacitance
input/output capacitance
power dissipation capacitance per package
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package
Information”.
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
December 1990
2
Philips Semiconductors
Product specification
8-bit universal shift register; 3-state
PIN DESCRIPTION
PIN NO.
1, 19
2, 3
7, 13, 6, 14, 5, 15, 4, 16
8, 17
9
10
11
12
18
20
SYMBOL
S
0
, S
1
OE
1
, OE
2
I/O
0
to I/O
7
Q
0
, Q
7
MR
GND
D
SR
CP
D
SL
V
CC
NAME AND FUNCTION
mode select inputs
3-state output enable inputs (active LOW)
74HC/HCT299
parallel data inputs or 3-state parallel outputs (bus driver)
serial outputs (standard output)
asynchronous master reset input (active LOW)
ground (0 V)
serial data shift-right input
clock input (LOW-to-HIGH, edge-triggered)
serial data shift-left input
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
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