K4S560432J
K4S560832J
K4S561632J
Synchronous DRAM
256Mb J-die SDRAM Specification
54 TSOP-II
with Lead-Free & Halogen-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE
CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-
WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-
OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT
GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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K4S560432J
K4S560832J
K4S561632J
Synchronous DRAM
Table of Contents
1.0 Features ....................................................................................................................................... 4
2.0 General Description ................................................................................................................... 4
3.0 Ordering Information .................................................................................................................. 4
4.0 Package Physical Dimension ................................................................................................... 5
5.0 Functional Block Diagram......................................................................................................... 6
6.0 Pin Configuration (Top view) ..................................................................................................... 7
7.0 Pin Function Description ........................................................................................................... 7
8.0 Absolute Maximum Ratings........................................................................................................8
9.0 DC Operating Conditions ........................................................................................................... 8
10.0 Capacitance............................................................................................................................... 8
11.0 DC Characteristics (x4, x8) ......................................................................................................9
12.0 DC Characteristics (x16) ........................................................................................................10
13.0 AC Operating Test Conditions ...............................................................................................11
14.0 Operating AC Parameter ........................................................................................................11
15.0 AC Characteristics ..................................................................................................................12
16.0 DQ Buffer Output Drive Characteristics ...............................................................................12
17.0 IBIS Specification .....................................................................................................................13
18.0 Simplified Truth Table ............................................................................................................15
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K4S560432J
K4S560832J
K4S561632J
Synchronous DRAM
Month
June
October
January
March
August
Year
2007
2007
2008
2008
2008
- Release 1.0 version SPEC
- Changed IDD current SPEC
- Revised typo of package dimension
- Added the comment of Halogen-free supporting
- Added 200Mhz speed
- Added Package pin out lead width
- Added 200MHz current SPEC
- Corrected font format
History
Revision History
Revision
1.0
1.1
1.2
1.21
1.22
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Rev. 1.22 August 2008
K4S560432J
K4S560832J
K4S561632J
Synchronous DRAM
16M x 4Bit x 4 Banks / 8M x 8Bit x 4 Banks / 4M x 16Bit x 4 Banks SDRAM
1.0 Features
•
•
•
•
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system clock.
Burst read single-bit write operation
DQM (x4,x8) & L(U)DQM (x16) for masking
Auto & self refresh
64ms refresh period (8K Cycle)
Lead-Free & Halogen-Free Package
RoHS compliant
•
•
•
•
•
•
•
2.0 General Description
The K4S560432J / K4S560832J / K4S561632J is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x
16,777,216 words by 4 bits / 4 x 8,388,608 words by 8bits / 4 x 4,194,304 words by 16bits, fabricated with SAMSUNG's high perfor-
mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible
on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to
be useful for a variety of high bandwidth, high performance memory system applications.
3.0 Ordering Information
Part No.
K4S560432J-U
*1
C/L75
K4S560832J-UC/L75
K4S561632J-UC/L50
K4S561632J-UC/L60
K4S561632J-UC/L75
16M x 16
Orgainization
64M x 4
32M x 8
Max Freq.
133MHz (CL=3)
133MHz (CL=3)
200MHz (CL=3)
166MHz (CL=3)
133MHz (CL=3)
LVTTL
54pin TSOP(II)
Lead-Free & Halogen-Free
*1
Interface
Package
Note 1 : 256Mb J-die SDR DRAMs support Lead-Free & Halogen-Free package with Lead-Free package code(-U).
Organization
64Mx4
32Mx8
16Mx16
Row Address
A0~A12
A0~A12
A0~A12
Column Address
A0-A9, A11
A0-A9
A0-A8
Row & Column address configuration
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K4S560432J
K4S560832J
K4S561632J
Synchronous DRAM
4.0 Package Physical Dimension
(0.80)
(0.50)
#54
#28
Unit : mm
10.16
±
0.10
(1.50)
(0.80)
0.665
±
0.05
0.210
±
0.05
1.00
±
0.10
22.22
±
0.10
(R
0.1
5)
(10°)
1.20 MAX
0.125
- 0.035
+0.075
(0.50)
#1
(1.50)
#27
(10°)
(10°)
11.76
±
0.20
(10.76)
0.05 MIN
0.
15
)
(0.71)
0.80TYP
[0.80
±
0.08]
(R
0.075 MAX
0.
25
)
(R
(R
0.
25
)
Detail A
Detail B
NOTE
1. ( ) IS REFERENCE
2. [ ] IS ASS’Y OUT QUALITY
Detail A
0.30
- 0.05
+0.10
Detail B
(0°
∼
8°)
0.35
- 0.05
+0.10
54Pin TSOP(II) Package Dimension
5 of 15
[
(10°)
[
(4°)
0.10 MAX
Rev. 1.22 August 2008
0.45 ~ 0.75
0.25TYP
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