a
PERFORMANCE FEATURES
ADSP-21060 Core Processor (.
. .
4)
480 MFLOPS Peak, 320 MFLOPS Sustained
25 ns Instruction Rate, Single-Cycle
Instruction Execution–Each of Four Processors
16 Mbit Shared SRAM (Internal to SHARCs)
4 Gigawords Addressable Off-Module Memory
Twelve 40 Mbyte/s Link Ports (Three per SHARC)
Four 40 Mbit/s Independent Serial Ports (One from
Each SHARC)
One 40 Mbit/s Common Serial Port
5 V and 3.3 V Operation
32-Bit Single Precision and 40-Bit Extended
Precision IEEE Floating Point Data Formats, or
32-Bit Fixed Point Data Format
IEEE JTAG Standard 1149.1 Test Access Port and
On-Chip Emulation
PACKAGING FEATURES
308-Lead Ceramic Quad Flatpack (CQFP)
2.05" (52 mm) Body Size
Cavity Up or Down, Configurable
Low Profile, 0.160" Height
Hermetic
25 Mil (0.65 mm) Lead Pitch
29 Grams (typical)
JC
= 0.36 C/W
GENERAL DESCRIPTION
CPA
SPORT 1
TDI
Quad-SHARC
DSP Multiprocessor Family
AD14060/AD14060L
FUNCTIONAL BLOCK DIAGRAM
CS
TIMEXP
LINK 1
LINK 3
LINK 4
FLAG
2,0
IRQ
2-0
CS
TIMEXP
LINK 1
LINK 3
LINK 4
LINK 0
LINK 2
LINK 5
TDO
LINK 0
LINK 2
LINK 5
TDI
®
EBOOT,
LBOOT,
BMS
EMU
CLKIN
EBOOT,
LBOOT,
BMS
EMU
CLKIN
(ID
2-0
= 1)
SPORT 0
TCK, TMS, TRST
FLAG
1
(ID
2-0
= 2)
RESET
AD14060/
AD14060L
SHARC BUS (
ADDR
31-0
,
DATA
47-0
,
MS
3-0
,
RD, WR, PAGE, ADRCLK, SW, ACK,
SBTS, HBR, HBG, REDY, BR
6-1
, RPBA, DMAR
1.2
, DMAG
1.2
)
FLAG
3
EBOOT,
LBOOT,
BMS
SPORT 0
TCK, TMS, TRST
FLAG
1
EBOOT,
LBOOT,
BMS
FLAG
3
EMU
CLKIN
CPA
SPORT 1
TDO
SHARC_D
(ID
2-0
= 4)
FLAG
2,0
CS
TIMEXP
LINK 1
LINK 3
LINK 4
IRQ
2-0
The AD14060/AD14060L Quad-SHARC is the first in a family
of high performance DSP multiprocessor modules. The core of
the multiprocessor is the ADSP-21060 DSP microcomputer.
The AD14060/AD14060L modules have the highest perfor-
mance —density and lowest cost—performance ratios of any in
their class. They are ideal for applications requiring higher levels
of performance and/or functionality per unit area.
The AD14060/AD14060L takes advantage of the built-in multi-
processing features of the ADSP-21060 to achieve 480 peak
MFLOPS with a single chip type, in a single package. The on-
chip SRAM of the DSPs provides 16 Mbits of on-module
shared SRAM. The complete shared bus (48 data, 32 address)
is also brought off-module for interfacing with expansion
memory or other peripherals.
The ADSP-21060 link ports are interconnected to provide
direct communication among the four SHARCs as well as high
speed off-module access. Internally, each SHARC has a direct
link port connection. Externally, each SHARC has a total of
120 Mbytes/s link port bandwidth.
Multiprocessor performance is enhanced with embedded power
and ground planes, matched impedance interconnect, and opti-
mized signal routing lengths and separation. The fully tested
and ready-to-insert multiprocessor also significantly reduces
board space.
SHARC is a registered trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1997
FLAG
2,0
TIMEXP
LINK 1
LINK 3
LINK 4
IRQ
2-0
CS
LINK 0
LINK 2
LINK 5
TDI
LINK 0
LINK 2
LINK 5
TDO
SHARC_C
(ID
2-0
= 3)
SPORT 0
TCK, TMS, TRST
FLAG
1
FLAG
3
TDI
CPA
SPORT 1
EMU
CLKIN
RESET
RESET
SPORT 0
TCK, TMS, TRST
FLAG
1
FLAG
3
TDO
SHARC_A
SHARC_B
CPA
SPORT 1
RESET
FLAG
2,0
IRQ
2-0
AD14060/AD14060L
DETAILED DESCRIPTION
Architectural Features
ADSP-21060 Core
The AD14060/AD14060L is based on the powerful ADSP-21060
(SHARC) DSP chip. The ADSP-21060 SHARC combines a
high performance floating-point DSP core with integrated, on-
chip system features including a 4 Mbit SRAM memory, host
processor interface, DMA controller, serial ports, and both link
port and parallel bus connectivity for glueless DSP multiprocess-
ing, (see Figure 1). It is fabricated in a high speed, low power
CMOS process, and has a 25 ns instruction cycle time. The arith-
metic/ logic unit (ALU), multiplier and shifter all perform single-
cycle instructions, and the three units are arranged in parallel,
maximizing computational throughput.
The SHARC features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data, and the pro-
gram memory (PM) bus transfers both instructions and data.
There is also an on-chip instruction cache which selectively
caches only those instructions whose fetches conflict with the
PM bus data accesses. This combines with the separate program
and data memory buses to enable three-bus operation for fetch-
ing an instruction and two operands, all in a single cycle. The
SHARC also contains a general purpose data register file, which
is a 10-port, 32-register (16 primary, 16 secondary) file. Each
SHARC’s core also implements two data address generators
(DAGs), implementing circular data buffers in hardware. The
DAGs contain sufficient registers to allow the creation of up to
32 circular buffers. The 48-bit instruction word accommodates a
variety of parallel operations, for concise programming. For ex-
ample, the ADSP-21060 can conditionally execute a multiply, an
add, a subtract, and a branch, all in a single instruction.
CORE PROCESSOR
TIMER
INSTRUCTION
CACHE
32 x 48-BIT
ADDR
ADDR
The SHARCs contain 4 Mbits of on-chip SRAM each, orga-
nized as two blocks of 2 Mbits, which can be configured for
different combinations of code and data storage. The memory
can be configured as a maximum of 128K words of 32-bit data,
256K words of 16-bit data, 80K words of 48-bit instructions (or
40-bit data), or combinations of different word sizes up to
4 megabits. A 16-bit floating-point storage format is supported
which effectively doubles the amount of data that may be stored
on chip. Conversion between the 32-bit floating point and 16-
bit floating point formats is done in a single instruction. Each
memory block is dual-ported for single-cycle, independent
accesses by the core processor and I/O processor or DMA con-
troller. The dual-ported memory and separate on-chip buses
allow two data transfers from the core and one from I/O, all in a
single cycle.
Shared Memory Multiprocessing
The AD14060/AD14060L takes advantage of the powerful
multiprocessing features built into the SHARC. The SHARCs are
connected to maximize the performance of this cluster-of-four
architecture, and still allow for off-module expansion. The
AD14060/AD14060L in itself is a complete shared memory
multiprocessing system, as shown in Figure 3. The unified ad-
dress space of the SHARCs allows direct interprocessor ac-
cesses of each SHARCs’ internal memory. In other words, each
SHARC can directly access the internal memory and IOP registers
of each of the other SHARCs by simply reading or writing to the
appropriate address in multiprocessor memory space (see Figure
2)—this is called a
direct read or direct write.
DUAL-PORTED SRAM
BLOCK 0
BLOCK 1
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
DATA
DATA
JTAG
TEST AND
EMULATION
7
I/O PORT
DATA
DATA
ADDR
ADDR
DAG1
8 x 4 x 32
DAG2
8 x 4 x 24
PROGRAM
SEQUENCER
24
32
IOD
48
IOA
17
PM ADDRESS BUS
DM ADDRESS BUS
EXTERNAL
PORT
ADDR BUS
MUX
MULTIPROCESSOR
INTERFACE
32
PM DATA BUS
48
40/32
DATA BUS
MUX
HOST PORT
48
BUS
CONNECT
(PX)
DM DATA BUS
DATA
REGISTER
FILE
MULTIPLIER
16 x 40-BIT
IOP
REGISTERS
(
MEMORY MAPPED)
BARREL
SHIFTER
ALU
CONTROL,
STATUS, AND
DATA BUFFERS
DMA
CONTROLLER
SERIAL PORTS
(2)
LINK PORTS
(6)
4
6
6
36
I/O PROCESSOR
Figure 1. ADSP-21060 Processor Block Diagram (Core of the AD14060)
–2–
REV. A
AD14060/AD14060L
0x0000 0000
0x0040 0000
BANK 0
DRAM
(OPTIONAL)
INTERNAL
MEMORY
SPACE
(INDIVIDUAL
SHARCs)
IOP REGISTERS
0x0002 0000
NORMAL WORD ADDRESSING
0x0004 0000
SHORT WORD ADDRESSING
0x0008 0000
INTERNAL MEMORY SPACE
OF SHARC_A
ID=001
0x0010 0000
INTERNAL MEMORY SPACE
OF SHARC_B
ID=010
0x0018 0000
INTERNAL MEMORY SPACE
OF SHARC_C
ID=011
0x0020 0000
INTERNAL MEMORY SPACE
OF SHARC_D
ID=100
0x0028 0000
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=101
BANK 2
MS
2
BANK 1
MS
1
MS
0
INTERNAL
TO AD14060
MULTIPROCESSOR
MEMORY SPACE
EXTERNAL
MEMORY
SPACE
BANK 3
MS
3
EXTERNAL
TO AD14060
0x0030 0000
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=110
0x0038 0000
BROADCAST WRITE
TO ALL
ADSP-2106xs
0x003F FFFF
NONBANKED
BANK SIZE IS
SELECTED BY
MSIZE BIT FIELD OF
SYSCON
REGISTER.
NORMAL WORD ADDRESSING: 32-BIT DATA WORDS
48-BIT INSTRUCTION WORDS
SHORT WORD ADDRESSING: 16-BIT DATA WORDS
0xFFFF FFFF
Figure 2. AD14060/AD14060L Memory Map
SYSTEM EXPANSION
SHARC_A
1X CLOCK
CLKIN
RESET
RPBA
CPA
LINKS 1, 3, & 4;
IRQ
2-0
;
FLAGS 2 & 0;
TIMEXP,
SPORT1
SHARC_B
LINKS 1, 3, & 4;
IRQ
2-0
;
FLAGS 2 & 0;
TIMEXP,
SPORT1
ADDR
31-0
DATA
47-0
RD
WR
ACK
MS
3-0
PAGE
SBTS
SW
ADRCLK
CS
HBR
HBG
REDY
BR
1-6
BOOTSELECT A
BOOTSELECT BCD
DMAR1,2
DMAG1,2
SPORT0
FLAG1
JTAG
AD14060/AD14060L
(QUAD PROCESSOR
CLUSTER)
SHARC_D
LINKS 1, 3, & 4;
IRQ
2-0
;
FLAGS 2 & 0;
TIMEXP,
SPORT1
SHARC_C
LINKS 1, 3, & 4;
IRQ
2-0
;
FLAGS 2 & 0;
TIMEXP,
SPORT1
Figure 3. Complete Shared Memory Multiprocessing System
REV. A
–3–
AD14060/AD14060L
Bus arbitration is accomplished with the on-SHARC arbitration
logic. Each SHARC has a unique ID, and drives the Bus-Request
(BR) line corresponding to its ID, while monitoring all others.
BR1–BR4
are used within the AD14060/AD14060L, while
BR5
and
BR6
can be used for expansion. All bus requests (BR1–BR6)
are included in the module I/O.
Two different priority schemes, fixed and rotating, are available
to resolve competing bus requests. The RPBA pin selects which
scheme is used: when RPBA is high, rotating priority bus arbitra-
tion is selected, and when RPBA is low, fixed priority is selected.
Table I. Rotating Priority Arbitration Example
Cycle
1
2
3
4
5
ID1
M
4
4
5 BR
1 BR
Hardware Processor IDs
ID2
ID3
ID4 ID5 ID6
1
5 BR
5 BR
M
2
2 BR
M-BR
M
1
3
3
1
1
2
4
4
2
2
3
5
5
Initial Priority Assignments
3
3
4 BR
M
Final Priority Assignments
off-module memory and peripherals (see Figure 5). This port
consists of the complete external port bus of the SHARC, bused
together in common among the four SHARCs.
The 4-gigaword off-module address space is included in the
ADSP-14060’s unified address space. Addressing of external
memory devices is facilitated by each SHARC internally de-
coding the high order address lines to generate memory bank
select signals. Separate control lines are also generated for sim-
plified addressing of page-mode DRAM. The AD14060/
AD14060L also supports programmable memory wait states and
external memory acknowledge controls to allow interfacing to
DRAM and peripherals with variable access, hold and disable
time requirements.
Link Port I/O
NOTES
1–5 = Assigned Priority.
M = Bus Mastership (in that cycle).
BR = Requesting Bus Mastership with BRx.
Each individual SHARC features six 4-bit link ports that facili-
tate SHARC-to-SHARC communication and external I/O inter-
facing. Each link port can be configured for either 1× or 2×
operation, allowing each to transfer either 4 or 8 bits per cycle.
The link ports can operate independently and simultaneously,
with a maximum bandwidth of 40 MBytes/s each, or a total of
240 MBytes/s per SHARC.
The AD14060/AD14060L optimizes the link port connections
internally, and brings a total of twelve of the link ports off-mod-
ule for user-defined system connections. Internally, each SHARC
has a connection to the other three SHARCs with a dedicated
link port interface. Thus, each SHARC can directly interface
with its nearest and next-nearest neighbor. The remaining three
link ports from each SHARC are brought out independently
from each SHARC. A maximum of 480 MBytes/s link port
bandwidth is then available off of the AD14060/AD14060L.
The link port connections are detailed in Figure 4.
Bus mastership is passed from one SHARC to another during a
bus transition cycle.
A bus transition cycle only occurs when the
current bus master deasserts its BR line and one of the slave
SHARCs asserts its BR line. The bus master can therefore re-
tain bus mastership by keeping its BR line asserted. When the
bus master deasserts its BR line, and no other BR line is as-
serted, then the master will not lose any bus cycles. When more
than one SHARC asserts its BR line, the SHARC with the
highest priority request becomes bus master on the following
cycle. Each SHARC observes all of the BR lines, and therefore
tracks when a bus transition cycle has occurred, and which
processor has become the new bus master. Master processor
changeover incurs only one cycle of overhead. An example bus
transition sequence is shown in Table I.
Bus locking is possible, allowing indivisible read-modify-write
sequences for semaphores. In either the fixed or rotating priority
scheme, it is also possible to limit the number of cycles the
master can control the bus. The AD14060/AD14060L also
provides the option of using the Core Priority Access (CPA)
mode of the SHARC. Using the CPA signal allows external bus
accesses by the core processor of a slave SHARC to take priority
over ongoing DMA transfers. Also, each SHARC can broadcast
write to all other SHARCs simultaneously, allowing the imple-
mentation of reflective semaphores.
The bus master can communicate with slave SHARCs by writ-
ing messages to their internal IOP registers. The MSRG0–
MSRG7 registers are general-purpose registers that can be used
for convenient message passing, semaphores and resource shar-
ing between the SHARCs. For message passing, the master
communicates with a slave by writing and/or reading any of the
eight message registers on the slave. For vector interrupts, the
master can issue a vector interrupt to a slave by writing the
address of an interrupt service routine to the slave’s VIRPT
register. This causes an immediate high priority interrupt on the
slave which, when serviced, will cause it to branch to the speci-
fied service routine.
1
5
3
4
5
2
1
SHARC_A
2
SHARC_B
3
4
0
0
1
3
4
2
2
0
0
1
SHARC_D
5
5
SHARC_C
3
4
Figure 4. Link Port Connections
Link port 4, the boot link port, is brought off independently
from each SHARC. Individual booting is then allowed, or
chained link port booting is possible as described under “Link
Port Booting.”
Link port data is packed into 32-bit or 48-bit words, and can
be directly read by the SHARC core processor or DMA-
transferred to on-SHARC memory.
Each link port has its own double-buffered input and output
registers. Clock/acknowledge handshaking controls link port
Off-Module Memory and Peripherals Interface
transfers. Transfers are programmable as either transmit or
The AD14060/AD14060L’s external port provides the interface to
receive.
REV. A
–4–
AD14060/AD14060L
AD14060/
AD14060L
1x
CLOCK
RESET
CLKIN
RESET
RPBA
ADDR
31–0
DATA
47–0
RD
WR
ACK
MS
3–0
BMS
PAGE
SBTS
SW
ADRCLK
CS
HBR
HBG
REDY
SERIALS
LINKS
DISCRETES
CPA
BR
2–6
BR
1
ADDR
5
DATA
ADDR
DATA
OE
WE
ACK
CS
CS
ADDR
DATA
GLOBAL
MEMORY
AND
PERIPHERALS
(OPTIONAL)
CONTROL
BOOT
EPROM
(OPTIONAL)
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
ADSP-2106x #5
(OPTIONAL)
ADDR
31–0
CLKIN
RESET
RPBA
101
3
ID
2–0
CONTROL
DATA
47–0
CPA
BR
1, 2, 3, 4, 6
BR
5
5
ADSP-2106x #6
(OPTIONAL)
CLKIN
RESET
RPBA
110
3
ID
2–0
ADDR
31–0
DATA
47–0
CONTROL
CPA
BR
1–5
BR
6
5
Figure 5. Optional System Interconnections
REV. A
–5–
FPGA/CPLD
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