CY28405
CK409-Compliant Clock Synthesizer
Features
• Supports Intel Springdale/Prescott (CK409)
• Selectable CPU frequencies
• 3.3V power supply
• Nine copies of PCI clock
• Four copies 3V66 clock with one optional VCH
• Two copies 48-MHz USB clock
• Two copies REF clock
• Three differential CPU clock pairs
• Dial-A-Frequency
®
• Supports SMBus/I
2
C Byte, Word, and Block Read/Write
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 48-pin SSOP package
CPU
x3
3V66
x4
PCI
x9
REF
x2
48M
x2
Block Diagram
Pin Configuration
**FS_A/REF_0
**FS_B/REF_1
VDD_REF
VDD_REF
REF[0:1]
XIN
XOUT
VDD_CPU
VSS_REF
CPUT[0:1,ITP], CPUC[0:1,ITP]
*FS_C/PCIF0
*FS_D/PCIF1
*FS_E/PCIF2
VDD_PCI
VSS_PCI
PCI0
PCI1
VDD_3V66
3V66_[0:2]
PCI2
PCI3
VDD_PCI
VDD_PCI
PCIF[0:2]
VSS_PCI
PCI[0:5]
PCI4
PCI5
RESET#/PD#
DOT_48
3V66_3/VCH
USB_48
VSS_48
VDD_48MHz
VDD_48
DOT_48
USB_48
XIN
XOUT
XTAL
OSC
PLL 1
PLL Ref Freq
Divider
Network
FS_[A:E]
VTT_PWRGD#
IREF
SELVCH
PLL2
2
MODE
PD#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDA
VSSA
IREF
CPUT_ITP
CPUC_ITP
VSS_CPU
CPUT1
CPUC1
VDD_CPU
CPUT0
CPUC0
VSS
DNC***
DNC***
VDD
VTT_PWRGD#
SDATA
SCLK
3V66_0
3V66_1
VSS_3V66
VDD_3V66
3V66_2/MODE*
3V66_3/VCH/SELVCH**
~
SSOP-48
* 150k Internal Pull-up
** 150k Internal Pull-down
*** Do Not Connect
CY28405
SDATA
SCLK
I
2
C
Logic
WD
Timer
RESET#
Cypress Semiconductor Corporation
Document #: 38-07512 Rev. *B
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised June 16, 2004
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CY28405
Pin Description
Pin No.
1, 2
REF(0:1)
Name
Type
O, SE
I
I
Description
Reference Clock.
3.3V 14.318-MHz clock output.
3.3V LVTTL latched input for CPU frequency selection.
Crystal Connection or External Reference Frequency Input.
This pin
has dual functions. It can be used as an external 14.318-MHz crystal
connection or as an external reference frequency input.
Crystal Connection.
Connection for an external 14.318-MHz crystal
output.
CPU Clock Output.
Differential CPU clock outputs.
CPU Clock Output.
Differential CPU clock outputs.
Do Not Connect.
O, SE
I/O, SE
PD
I/O, SE
PU
66-MHz Clock Output.
3.3V 66-MHz clock from internal VCO.
48- or 66-MHz Clock Output.
3.3V selectable through external SELVCH
strapping resistor and SMBus to be 66-MHz or 48-MHz. Default is 66-MHz.
0 = 66 MHz, 1 = 48 MHz
66-MHz Clock Output.
3.3V 66-MHz clock from internal VCO. Reset or
Power-down Mode Select. Selects between RESET# output or PWRDWN#
input for the PWRDWN#/RESET# pin. Default is RESET#. 0 = PD#, 1 =
RESET
Free Running PCI Output.
33-MHz clocks divided down from 3V66.
PCI Clock Output.
33-MHz clocks divided down from 3V66.
Fixed 48-MHz clock output.
Fixed 48-MHz clock output.
Current Reference.
A precision resistor is attached to this pin which is
connected to the internal current reference.
3.3V LVTTL input for Power-down# active LOW.
Watchdog Timeout
Reset Output
3.3V LVTTL input is a level sensitive strobe used to latch the FS[A:E]
input (active LOW).
SMBus compatible SDATA.
SMBus compatible SCLOCK.
3.3V Power supply for PLL.
Ground for PLL.
3.3V Power supply for outputs.
1, 2, 7, 8, 9 FS_A, FS_B, FS_C,
FS_D, FS_E
4
XIN
5
39, 42, 45
38, 41, 44
36, 35
30, 29
25
XOUT
CPUT(0:1,ITP)
CPUC(0:1,ITP)
DNC
3V66(0:1)
3V66_3/VCH/SELVCH
O, SE
O, DIF
O, DIF
26
3V66_2/MODE
7, 8, 9
PCIF(0:2)
O, SE
O, SE
O, SE
O, SE
I
I/O, PU
I
I/O
I
PWR
GND
PWR
12, 13, 14, PCI(0:5)
15, 18, 19
22
21
46
20
33
32
31
48
47
USB_48
DOT_48
IREF
RESET#/PD#
VTT_PWRGD#
SDATA
SCLK
VDDA
VSSA
3, 10, 16, VDD(REF,PCI,48,3V66,C
24, 27, 34, PU,ITP)
40
6, 11, 17, VSS(REF,PCI,48,3V66,
23, 28, 37, CPU,ITP)
43
GND
Ground for outputs.
Document #: 38-07512 Rev. *B
Page 2 of 19
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CY28405
MODE Select
The hardware strapping MODE input pin can be used to select
the functionality of the RESET#/PD# pin. The default (internal
pull up) configuration is for this pin to function as a RESET#
Watchdog output. When pulled LOW during device power-up,
the RESET#/PD# pin will be configured to function as a Power
Down input pin.
Frequency Select Pins
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A through FS_E inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled low by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FS_A through FS_E input values. For all logic
levels of FS_A through FS_E, VTT_PWRGD# employs a
one-shot functionality in that once a valid low on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#
and FS_A through FS_E transitions will be ignored.
Table 1. Frequency Selection Table
Input Conditions
FS_E
FSEL_4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FS_D
FSEL_3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS_C
FSEL_2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS_B
FSEL_1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS_A
FSEL_0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
100.7
100.2
108.0
101.2
Reserved
Reserved
Reserved
Reserved
125.7
130.3
133.6
134.2
134.5
148.0
Reserved
Reserved
Reserved
Reserved
167.4
170.0
175.0
180.0
185.0
190.0
100.9
133.9
200.9
Reserved
100.0
133.3
200.0
Reserved
3V66
67.1
66.8
72.0
67.5
Reserved
Reserved
Reserved
Reserved
62.9
65.1
66.8
67.1
67.3
74.0
Reserved
Reserved
Reserved
Reserved
55.8
56.7
58.3
60.0
61.7
63.3
67.3
67.0
67.0
Reserved
66.7
66.7
66.7
Reserved
PCI
33.6
33.4
36.0
33.7
Reserved
Reserved
Reserved
Reserved
31.4
32.6
33.4
33.6
33.6
37.0
Reserved
Reserved
Reserved
Reserved
27.9
28.3
29.2
30.0
30.8
31.7
33.6
33.5
33.5
Reserved
33.3
33.3
33.3
Reserved
VCO Freq.
805.6
801.6
864.0
809.6
Reserved
Reserved
Reserved
Reserved
754.2
781.6
801.6
805.2
807.0
888.0
Reserved
Reserved
Reserved
Reserved
669.6
680.0
700.0
720.0
740.0
760.0
807.2
803.4
803.6
Reserved
800.0
800.0
800.0
Reserved
Output Frequency
PLL Gear
Constants
(G)
24004009.32
24004009.32
24004009.32
24004009.32
Reserved
Reserved
Reserved
Reserved
32005345.76
32005345.76
32005345.76
32005345.76
32005345.76
32005345.76
Reserved
Reserved
Reserved
Reserved
48008018.65
48008018.65
48008018.65
48008018.65
48008018.65
48008018.65
24004009.32
32005345.76
48008018.65
Reserved
24004009.32
32005345.76
48008018.65
Reserved
Document #: 38-07512 Rev. *B
Page 3 of 19
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CY28405
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. The interface can also be
accessed during power-down operation.
Data Protocol
The clock driver serial protocol accepts Byte Write, Byte Read,
Block Write and Block Read operation from any external I
2
C
controller. For Block Write/Read operation, the bytes must be
accessed in sequential order from lowest to highest byte (most
significant bit first) with the ability to stop after any complete
byte has been transferred. For Byte Write and Byte Read
operations, the system controller can access individual
indexed bytes. The offset of the indexed byte is encoded in the
command code, as described in
Table 2.
The Block Write and Block Read protocol is outlined in
Table 3
while
Table 4
outlines the corresponding Byte Write and Byte
Read protocol. The slave receiver address is 11010010 (D2h).
Table 2. Command Code Definition
Bit
7
(6:0)
0 = Block Read or Block Write operation
1 = Byte Read or Byte Write operation
Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations, these bits
should be ‘0000000’
Description
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
2:8
9
10
11:18
19
20:27
28
29:36
37
38:45
46
....
....
....
....
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8-bit ‘00000000’ stands for
block operation
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
Data byte 0 – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data Byte N/Slave Acknowledge...
Data Byte N – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39:46
47
48:55
56
....
....
....
....
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8-bit ‘00000000’ stands for
block operation
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge
Data byte from slave – 8 bits
Acknowledge
Data byte from slave – 8 bits
Acknowledge
Data bytes from slave/Acknowledge
Data byte N from slave – 8 bits
Not Acknowledge
Stop
Block Read Protocol
Description
Document #: 38-07512 Rev. *B
Page 4 of 19
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CY28405
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
‘1xxxxxxx’ stands for byte operation, bits[6:0] of
the command code represents the offset of the
byte to be accessed
Acknowledge from slave
Data byte from master – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
‘1xxxxxxx’ stands for byte operation, bits[6:0]
of the command code represents the offset of
the byte to be accessed
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Data byte from slave – 8 bits
Not Acknowledge
Stop
Byte Read Protocol
Description
19
20:27
28
29
19
20
21:27
28
29
30:37
38
39
Byte 0: Control Register 0
Bit
7
6
@Pup
0
1
PCIF
PCI
Reserved
FS_E
FS_D
FS_C
FS_B
FS_A
Name
Reserved, Set= 0
PCI Drive Strength Override
0 = Force All PCI and PCIF Outputs to Low Drive Strength
1= Force All PCI and PCIF Outputs to High Drive Strength
Reserved, Set= 0
Power up latched value of FS_E pin
Power up latched value of FS_D pin
Power up latched value of FS_C pin
Power up latched value of FS_B pin
Power up latched value of FS_A pin
Description
5
4
3
2
1
0
0
HW
HW
HW
HW
HW
Byte 1: Control Register 1
Bit
7
6
5
4
3
2
1
0
@Pup
0
1
1
1
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
CPUT_ITP, CPUC_ITP
CPUT1, CPUC1
CPUT0, CPUC0
Name
Reserved, set = 0
Reserved, set = 1
Reserved, set = 1
Reserved, set = 1
Reserved, set = 1
CPUT/C_ITP Output Enable
0 = Disabled (three-state), 1 = Enabled
CPU(T/C)1 Output Enable,
0 = Disabled (three-state), 1 = Enabled
CPU(T/C)0 Output Enable
0 = Disabled (three-state), 1 = Enabled
Description
Document #: 38-07512 Rev. *B
Page 5 of 19
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