56855
Data Sheet
Technical Data
56800E
16-bit Digital Signal Controllers
DSP56855
Rev. 6
01/2007
freescale.com
56855 General Description
• 120 MIPS at 120MHz
• 24K x 16-bit Program SRAM
• 24K x 16-bit Data SRAM
• 1K x 16-bit Boot ROM
• Access up to 2M words of program memory or 8M
words of data memory
• Chip Select Logic for glueless interface to ROM and
SRAM
• Six (6) independent channels of DMA
• Enhanced Synchronous Serial Interface (ESSI)
• Two (2) Serial Communication Interfaces (SCI)
• General Purpose 16-bit Quad Timer with 1 external pin
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Computer Operating Properly (COP)/Watchdog Timer
• Time-of-Day (TOD)
• 100 LQFP package
• Up to 18 GPIO
6
V
DDIO
10
V
DD
4
V
SSIO
10
V
SS
V
DDA
4
V
SSA
JTAG/
Enhanced
OnCE
Program Controller
and
Hardware Looping Unit
Address
Generation Unit
16-Bit
DSP56800E Core
Data ALU
16 x 16 + 36
→
36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Bit
Manipulation
Unit
PAB
PDB
CDBR
CDBW
Memory
Program Memory
24,576 x 16 SRAM
Boot ROM
1024 x 16 ROM
Data Memory
24,576 x 16 SRAM
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
System
Bus
Control
DMA
6 channel
Core CLK
IPBus Bridge (IPBB)
IPWDB
Decoding
Peripherals
A0-20 [20:0]
D0-D15 [15:0]
RD Enable
WR Enable
CS0-CS3[3:0] or
GPIOA0-GPIOA3[3:0]
Bus Control
External Address
Bus Switch
External Data
Bus Switch
External Bus
Interface Unit
2 SCI ESSI0
or
or
GPIOE GPIOC
IPRDB
IPAB
DMA Requests
IPBus CLK
POR
3
CLKO
MODEA-C or
(GPIOH0-H2)
RSTO
RESET
System
COP/TOD CLK Integration
Module
Quad
Timer
or
GPIOG
Interrupt
Controller
COP/
Watch-
dog
Time
of
Day
Clock
Generator
OSC PLL
EXTAL
XTAL
4
6
IRQA
IRQB
56855 Block Diagram
56855 Technical Data, Rev. 6
Freescale Semiconductor
3
Part 1 Overview
1.1 56855 Features
1.1.1
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Core
Efficient 16-bit engine with dual Harvard architecture
120 Million Instructions Per Second (MIPS) at 120MHz core frequency
Single-cycle 16
×
16-bit parallel Multiplier-Accumulator (MAC)
Four (4) 36-bit accumulators including extension bits
16-bit bidirectional shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three (3) internal address buses and one (1) external address bus
Four (4) internal data buses and one (1) external data bus
Instruction set supports both DSP and controller functions
Four (4) hardware interrupt levels
Five (5) software interrupt levels
Controller-style addressing modes and instructions for compact code
Efficient C Compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/Enhanced OnCE debug programming interface
1.1.2
•
•
Memory
Harvard architecture permits up to three (3) simultaneous accesses to program and data memory
On-Chip Memory
— 24K
×
16-bit Program SRAM
— 24K
×
16-bit Data SRAM
— 1K
×
16-bit Boot ROM
•
Off-Chip Memory Expansion (EMI)
— Access up to 2M words of program memory or 8M words of data memory
— Chip Select Logic for glue-less interface to ROM and SRAM
1.1.3
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Peripheral Circuits for 56855
General Purpose 16-bit Quad Timer with 1 external pin*
Two (2) Serial Communication Interfaces (SCI)*
Enhanced Synchronous Serial Interface (ESSI) module*
Computer Operating Properly (COP)/Watchdog Timer
JTAG/Enhanced On-Chip Emulation (EOnCE) for unobtrusive, real-time debugging
56855 Technical Data, Rev. 6
4
Freescale Semiconductor
56855 Description
•
•
•
Six (6) independent channels of DMA
Time-of-Day (TOD)
Up to 18 GPIO
* Each peripheral I/O can be used alternately as a General Purpose I/O if not needed
1.1.4
•
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Energy Information
Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs
Wait and Stop modes available
1.2 56855 Description
The 56855 is a member of the 56800E core-based family of controllers. It combines, on a single chip, the
processing power of a Digital Signal Processor (DSP) and the functionality of a microcontroller with a
flexible set of peripherals, creating an extremely cost-effective solution. Because of its low cost,
configuration flexibility, and compact program code, the 56855 is well-suited for many applications. The
56855 includes many peripherals that are especially useful for low-end Internet appliance applications
and low-end client applications such as telephony; portable devices; Internet audio; and point-of-sale
systems, such as noise suppression; ID tag readers; sonic/subsonic detectors; security access devices;
remote metering; sonic alarms.
The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C Compilers, enabling rapid
development of optimized control applications.
The 56855 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56855 also provides two external
dedicated interrupt lines, and up to 18 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.
The 56855 controller includes 24K words of Program RAM, 24K words of Data RAM and 1K of Boot
ROM. It also supports program execution from external memory.
This controller also provides a full set of standard programmable peripherals that include one Enhanced
Synchronous Serial Interface (ESSI), two Serial Communications Interfaces (SCI), and one Quad Timer.
The ESSI, SCIs, four chip selects and Quad Timer external output can be used as General Purpose
Input/Outputs when its primary function is not required.
56855 Technical Data, Rev. 6
Freescale Semiconductor
5
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