CT2553 / 2554 / 2555 / 2556
Advanced Integrated MUX (AIM) Hybrid
FOR MIL-STD-1553
Features
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Second Source Compatible to the BUS-61553
Complete Integrated MUX Including:
•
Low Power Dual Transceiver
•
BC/RTU/MT Protocol
•
8K x 16 Shared Ram
•
Interrupt Logic
Compatible with MIL-STD- 1750 and other Standard CPUs
DIP or Flatpack Hybrid
Minimizes CPU Overhead
Provides Memory Mapped 1553 Interface
On-Line & Off-Line Self-Test
PCs Development Tools Available
SEAFAC Tested
MIL-PRF-38534 compliant circuits available
DESC SMD #5962–88692 Pending
Packaging – Hermetic Metal
•
78 Pin, 2.1" x 1.87" x .25" Plug-In type package
•
82 Lead, 2.2" x 1.61" x .18" Flat package
CIRCUIT TECHNOLOGY
www.aeroflex.com
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General Description
Aeroflex’s CT2553 Advanced Integrated Mux (AIM) Hybrid is a complete MIL-STD-1553 Bus
Controller (BC), Remote Terminal Unit (RTU), and Bus Monitor (MT) device. Packaged in a single
78 pin DIP package, the CT2553 contains dual low-power transceivers, complete BC/RTU/MT
protocol logic, a MIL-STD-1553-to-host interface unit and an 8K x 16 RAM.
Using an industry standard dual transceiver and standard status and control signals, the CT2553
simplifies system integration at both the MIL-STD-1553 and host processor interface levels.
All 1553 operations are controlled through the CPU access to the shared 8K x 16 RAM. To ensure
maximum design flexibility, memory control lines are provided for attaching external RAM to the
CT2553 Address and Data Buses and for disabling internal memory; the total combined memory
space can be expanded to 64K x16. All 1553 transfers are entirely memory-mapped; thus the CPU
interface requires minimal hardware and/or software support.
The CT2553 operates over the full military -55°C to +125°C temperature range. Available screened
to MIL-STD883, the CT2553 is ideal for demanding military and industrial microprocessor to 1553
interface applications.
See "Ordering Information" (last sheet) for CT2554, CT2555 & CT2556.
eroflex Circuit T
echnology
– Data Bus Modules For The Future © SCDCT2553 REV B 8/6/99
Q1553-2
INH
CLOCK IN
MSTRCLR
TRANSCEIVER A
8
1
TX
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DATA
BUS A
2
4
3
TX
TRANSFORMER A
DECODER
STRBD
READYD
RD/WR
CHANNEL A
ENCODER/
MEMORY
TIMING
SELECT
RX
RX
CPU
TIMING
MEM/REG
768µs
TIMEOUT
PROTOCOL
CONTROLLER
CONTENTION
RESOLVER
INTERRUPT
GENERATOR
EXTEN
EXTLD
INT
2
INH
A15 - A00
Q1553-2
8
1
TX
D15 - D00
DATA
BUS B
2
4
3
TX
CHANNEL B
ENCODER/
DECODER
TRANSFORMER B
8K X 16
SHARED RAM
RTADR0
RTADR1
RTADR2
RX
RX
RAM
PARITY
CHECKER
RT ADDR
RTADR3
RTADRP
RTADR4
RTPARERR
TRANSCEIVER B
Note: The Watch-Dog Time Out (768µs TYP.) is built in.
SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700
Figure 1 – CT2553 Block Diagram
Values at nominal Power Supply Voltages unless otherwise specified
PARAMETER
Receiver
Differential Input Voltage
Differential Input Impedance
CMRR
Transmitter (Direct Coupled)
Differential Output Voltage
Output Rise and Fall Times
Output Offset Voltage
Logic*
V
IH
V
IL
Clock
Power Supplies
+5V (Logic)
-15VA (Channel A Transceiver)
-15VB (Channel B Transceiver)
+5VA (Channel A)
+5VB (Channel B)
Current Drain* (Total Package)
+5V (Idle)
-15V (Idle)
+5V (25% Duty Cycle)
-15V (25% Duty Cycle)
Temperature Range
Operating (Case)
Storage
Physical Characteristics
Size
78 pin DDIP
82 pin flatpack
* See Table 7 for pin loading characteristics.
VALUE
40 max
7 min
40 min
6.0 min, 9.0 max
100 min, 300 max
±90 max
2.2 min
0.8 max
16
+5±5%
-15±10%
-15±10%
+5±5%
+5±5%
(TYP)/max
(85)/170
(45)/80
(85)/170
(80)/130
−
55 to +125
−
65 to +150
UNITS
Vp-p
K
Ω
db
Vp-p
nsec
mV
V
V
MHZ
V
V
V
V
V
mA
mA
mA
mA
°C
°C
2.1 x 1.87 x 0.25
(53 x 47.5 x 6.4)
2.19 x 1.6 x 0.175
(55.6 x 40.6 x 4.34)
in
(mm)
in
(mm)
Table 1 – CT2553 Specifications
GENERAL
The CT2553 is a complete MIL-STD-1553 bus
interface unit containing dual low-power
transceivers; Bus Controller (BC), Remote
Terminal (RTU), and Bus Monitor (MT) protocol
logic; 8K x 16-bit pseudo dual port RAM; and
memory management arbitration control circuitry.
The host processor interface consists of standard
control and interrupt signals, memory expansion
capability and non-multiplexed address and data
buses.
Control of the CT2553 is accomplished entirely
through the use of three internal registers and the
3
shared RAM. Transfers to and from the CT2553
are executed on a word-by-word basis ensuring
minimal wait time if contention occurs.
The specific mods of operation (1553
BC/RTU/MT) is software programmable. Memory
is configured into unique control and data block
areas based on the 1553 mode of operation.
External registers are also supported by the
CT2553 for manipulation of user data. In addition,
the CT2553 provides dynamic, online and
software initiated self-test capabilities.
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SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700
INTERFACING
The CT2553 is compatible with most common
microprocessors including, but not limited to, the
Motorola 680 x 0, the Intel 808x, Zilog Z800x and
MIL-STD-1750 processors.
Interfacing the CT2553 to the MIL-STD-1553
Data Bus requires two Q1553-2 pulse
transformers and an external 16 MHz clock (See
Figure 2). Tri-state buffers are used to isolate the
CPU's data and address lines.
External RAM can be used instead of or in
conjunction with the CT2553's internal 8K x 16
bits. The external RAM used by the CT2553 can
be any standard static memory with an access
time of < 55ns. The external RAM can be
expanded to 64K x 16.
Two control signals, MEMENA-IN (pin 69) and
MEMENMA-OUT (pin 31) are provided in
addition to the standard memory I/O signals for
internal/external memory access control (See
Figures 3-5. MEMEN-OUT and MEMEN-IN
should be tied together for Internal Memory Only
configuration. Memory CS signals can be
generated for configurations using external
memory.
MEMORY MANAGEMENT
Memory can be configured to support two AREAs
(A and B), each with an independent sequential
stack and pointers for manipulating 1553
message and control data. The CPU can access
the shared RAM while 1553 message transfers
are taking place. Arbitration of the RAM is
automatically implemented in a manner
transparent to the subsystem (See Figures
28-31). Variable Length DATA BLOCKS are also
stored in the shared RAM and can be addressed
by setting pointers residing in Area A, Area B or
both.
For BC/RTU operation, each area contains a
Descriptor Stack and Stack Pointer (See Figures
6 and 7). BC operation further maintains a
Message Count for each area (number of 1553
messages per frame). RTU operation maintains a
data block address Look-Up Table for each area.
MT operation utilizes a single Stack Pointer to
indicate the starting address for storage of
received words and associated identification
Words.
CURRENT AREA ASSIGNMENT/SWAPPING.
Current area status (currently available to the
1553 terminal) is Software programmable by the
host; the unassigned area automatically assumes
non-current area status. Both areas are always
addressable by the host. Swapping of the Current
Area can be done following message transfers for
user operations such as exception handling or
multiple buffering of 1553 data.
The host selects the Current Area by writing to
the CT2553’s Configuration Register with bit 13
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set to the appropriate logic level (0 for area A or 1
for area B). Internal circuitry ensures that the
swapping of Current Area Status does not occur
during an ongoing message transfer (See
Configuration Register).
DESCRIPTOR
STACK
(BC/RTU).
The
DESCRIPTOR STACK (DS) is divided into 64
entries. Each stack entry contains four words
which refer to one 1553 message. The Block
Status Word (BSW) indicates the physical bus on
which the message was received (RTU mode),
reports whether or not an error was detected
during message transfer and indicates message
completion (See Figure 8).
The user-supplied Time Tag word is loaded at the
start of a message transfer and is updated at the
end of the transfer (See Time Tagging).
4
SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700
RD/WR
(DIR)
DATA
D0 - D15
(OE) (54LS245)
IOEN
ROM
RAM
I/O
(SEE NOTE 1)
MEMENA-IN
(OE) (54LS244)
CPU
ADDRESS
A0 - A12
13
MEMENA-OUT
16
RD/WR
36
51
RTADP
RTADDRESS
8
73
31
40
78
TX/RX-A
TX/RX-A
1
2
3
7
6
5
4
+
–
69
BUS-25679
CT2553
8
ADDRESS
DECODER
POR
(SEE NOTE 2)
MSTRCLR
20
71
59
TX/RX-B
TX/RX-B
1
2
3
7
6
5
4
+
–
SELECT
MEM/REG
(54LS04)
STRBD
74
33
3
34
2
+5V
-15V
BUS-25679
READYD
INT
75
12
72
13
15
ILLCMD
+5V
SA/MC-0
SA/MC-1
SA/MC-2
SA/MC-3
SA/MC-4
T/R
BCSTRCV
LMC
ILLEGALIZATION
PROM
(OPTIONAL)
HOST PROCESSOR
MEMOE
30
52
54
16MHz
CLOCK
32
53
57
XX
17
1553 INTERFACE
Figure 2 – CT2553 Example Interconnection
Aeroflex Circuit Technology
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SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700
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