®
A DC-AC Isolated Battery Inverter
Using the HIP4082
Application Note
February 2003
AN9611.1
Author: George E. Danz
WARNING
The HIP4082EVAL DC-AC Inverter contains HIGH
VOLTAGE and is a potential shock hazard. USE
CARE when DC power is connected.
adjustment avoids simultaneous MOSFET conduction
when switching from an upper MOSFET to a lower
MOSFET or vice-versa. It is the time period between turn-
off of an upper MOSFET gate, to turn-on of a lower
MOSFET gate and vice versa.
• The HIP4082 incorporates no charge pump, further
reducing size and cost. The dead-time setting resistor
connected between the DEL and V
SS
pins provides
possible dead-time settings from 0.1µs to 4.5µs thereby
extending the dead-time range provided by the HIP4080A
and HIP4081A ICs.
• The HIP4082 provides continuous on/off level-shift drive
signals for the upper MOSFETs. This eliminates concerns
that some users, particularly from the UPS industry, have
regarding poorer noise immunity of latched on/off upper
MOSFET gate control. Continuous on/off level-shift drive
signals for the upper MOSFETs results in slightly greater
power dissipation than latched gate drives. When an
upper MOSFET is turned off the common (phase)
connection between upper and lower MOSFETs falls
almost immediately to the ground potential, reducing the
voltage impressed across the level-shift transistor. Level-
shift power becomes significant only when an upper
MOSFET body diode current maintains the AHS and BHS
pins at the high voltage rail potential. This situation arises
only when freewheeling current keeps one of the upper
MOSFET body diodes conducting even though the gate
command for that MOSFET is off. This can happen when
a user directs freewheeling current to conduct in the upper
two bridge switches. It is better to direct all freewheeling
currents to flow in the lower two MOSFETs or their
associated body diodes, and minimize level-shift power
dissipation within the HIP4082. The level-shift power when
utilizing bottom circulation (freewheeling) is the product of
the level-shift current and the relatively low V
DD
(12V)
potential (not the high voltage bus potential).
• The HIP4082 is packaged in compact, 16 pin PDIP and
narrow body SOIC packages.
Introduction
The advent of the personal computer (PC), has created the
need for uninterruptible power supplies to insulate
computers from line dips and temporary outages that plague
PC reliability. In addition, numerous other applications exist
for DC to AC inverters including small tools or accessories
from a DC battery source in automobiles. There is a need,
too, for providing battery backup in the telephone industry for
20Hz ring generators.
The HIP4082 DC/AC Evaluation Board (subsequently
referred to as the “eval-board”) featuring the HIP4082 is one
way to increase the performance, while reducing cost of DC
to AC conversion. The topology chosen uses the HIP4082 to
provide a 60kHz, low voltage, square-wave to drive a small
isolation power transformer. The output of this transformer is
rectified, filtered, and the high voltage inverted again to
produce the desired low frequency (55Hz) output waveform.
(55Hz was chosen as a compromise between the 50Hz and
60Hz power standards.) A variable duty-cycle quasi-square-
wave output waveform was chosen over a sinusoidal
waveform for simplicity and cost-effectiveness. The 60kHz
frequency of the primary-side inverter minimizes cost
and size of the transformer, while the square-wave
output waveform minimizes the size of the secondary-side
rectifier filter.
Designers will provide modifications necessary to customize
the Evaluation Board for their specific applications.
HIP4082 Features
The combined features of the HIP4082 make it ideal for
Uninterruptible Power Supply (UPS), motor control, full
bridge power supply and switching power amplifier
applications. Switching power amplifier applications utilize
switching frequencies up to 200kHz.
The HIP4082 is an 80V N-Channel MOSFET Driver IC that
independently drives four N-Channel MOSFETs in a full
H-Bridge configuration. Whereas the HIP4082 is very similar
to the HIP4081A MOSFET driver, it is different in the
following important ways:
• The HIP4082 peak output drive current is 1.25A, which
reduces the need for adding series gate resistors when
driving medium to large MOSFETs.
• Only one delay time setting resistor is needed to adjust
dead-time when using the HIP4082. Proper dead-time
1
Design Summary
This DC-AC Inverter design presents one approach to
regulating the output voltage, protecting the inverter from
overcurrents and reducing output voltage when benign
overcurrents would tend to cause the system to overheat. A
neon light even warns users of high voltage when the unit is
energized.
The eval-board design shows how easy it is to design
inverters using the HIP4082. The eval-board is not the only
answer to UPS or portable battery inverter implementation.
The eval-board includes two inverters. The primary inverter
uses the HIP4082 to convert the 12V battery potential to
approximately 160V
DC
through transformer isolation. The
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Application Note 9611
second inverter converts the 160V
DC
voltage into a quasi-
square-wave representation of a sin-wave having a
frequency of 55Hz with a peak voltage matching the high
voltage DC bus potential. A simple feed forward technique
regulates the AC secondary voltage to 115V
AC
while the
battery varies over a range of approximately 11V to 15V.
(Through component modification, 230VAC is possible.)
The aforementioned features are similar to those of at least
one commercially available battery inverter (Radio Shack,
Catalog number 22-132A). Thermal limiting on the
evaluation unit is approximately 120W at ambient
temperatures to 30
o
C (a little lower than the competitive unit)
in order to allow the unit to be operated without a heat-
sinking enclosure. This allows users to probe various points
in order to provide a better understanding of circuit
operation.
Choosing Proper Dead-Time
The dead-time chosen for eliminating shoot-through currents
in the Q
1
-Q
4
and Q
2
-Q
3
MOSFET pairs is determined by the
value of R
2
connected between the DEL and V
SS
pins of the
HIP4082. The 15K value chosen provides approximately
0.5s of dead-time, sufficient to avoid shoot-through when
using RFP70N06 MOSFETs. Refer to the HIP4082 data
sheet, File Number 3676, Figure 16 for dead-time versus
delay resistance characteristics.
C2 (MAX)
9V
C1 FREQ.
118.28kHz
1
Primary Inverter Design
Input Filter
The primary-side inverter is comprised of a simple R-C input
filter. Capacitors, C
5
and C
6
provide a stiff, sag-free source
for the inverter bridge comprised of Q
1
through Q
4
as shown
in the schematic (see Appendix). To aid this process,
Resistor, R
37
and ceramic, non-inductive capacitor, C
7
,
parallel C
5
and C
6
. Automotive applications can be fraught
with voltage transients across the battery terminals. To
prevent these transients from exceeding the V
CC
voltage
ratings of the HIP4082 and other ICs on the primary inverter
section, R
7
, C
4
and D
3
clamp the V
CC
voltage to 16V or
less.
2
CH1 = 5V
CH2 = 5V
M = 2.5µs CH1
4.2V
FIGURE 1. 555 TIMER WAVEFORMS
C2 (MAX)
13.8V
C1 FREQ.
59.544kHz
LOW
SIGNAL
AMPL.
Primary Inverter Waveform Generation
To minimize the size of the secondary filter, a 50% duty cycle
square-wave was chosen for primary excitation. With a
nearly constant, low-ripple voltage, secondary filtering can
be minimized and ripple nearly eliminated. An inexpensive
Intersil ICM7555 timer was chosen. This timer, an improved
555 timer, reduces V
CC
to ground cross conduction current
spikes, thereby minimizing bias current requirements.
The timer, U
1
, operates in the astable mode, accomplished
by tying pins 2 and 6 of the timer together. The astable mode
requires only one resistor, R
1
, and one capacitor, C
3
. A 50%
duty-cycle square-wave is available at the “OUT” (pin 3)
terminal of timer, U
1
, as shown in Figure 1.
The timer ‘out’ pin drives the clock input, pin 3, of a CA4013
D-flip-flop connected as a divide by two circuit. To
accomplish the divide-by-two function, the QNOT output of
the flip-flop is fed back to its own data, D, input. The Q and
QNOT outputs of the CA4013 provide an exact 50% duty-
cycle square-wave at half the timer’s output frequency and
are applied to the ALI-BHI and the AHI-BLI gate control
inputs of the HIP4082 respectively as shown in Figure 2. The
ICM7555 clock frequency was chosen to be 120kHz so that
the primary inverter frequency would be 60kHz.
2
1
2
CH1 = 10V
CH2 = 10V
M = 2.5µs CH1
4.2V
FIGURE 2. INPUT WAVEFORMS TO THE HIP4082
Controlling di/dt and Switching Losses
Choice of gate resistor values for R
3
-R
5
, and R
8
is based
upon several factors. The gate resistors tailor the turn-on and
turn-off rise times of the power MOSFETs and the
commutating di/dt. The di/dt affects commutation losses and
body diode recovery losses. As di/dt increases, recovery
losses increase, but the commutation losses decrease. As
di/dt decreases, recovery losses decrease, and commutation
losses increase. Generally there is an ideal commutation di/dt
which minimizes the sum of these switching losses.
Application Note 9611
Inductances which are in series with each power MOSFET
also control di/dt. Stray inductance between the filter capacitor
and the positive and negative bus rails help reduce the
switching di/dt.
In the eval-board, no inductance is added to control the di/dt.
A small parasitic inductance exists naturally in the printed
circuit board and component layout. Secondary-side inverter
gate-to-source capacitors control the di/dt commutation rate.
Additionally, a snubber (R
38
-C
27
) was employed across the
inverter output terminals to control switching transients. The
gate-source capacitors help reduce the ringing at the
inverter bridge terminals associated with the output choke
employed to reduce EMI.
for Q
GATE
at 10V and at 20V. Obtain the equivalent C
GATE
by
taking the charge given in the data sheet for 10V and dividing
it by 10. Multiply the equivalent C
GATE
by the actual operating
V
CC
to get the actual Q
GATE
.
The third component of charge lost during each switching
cycle is that due to the recovery of the bootstrap diode. This
charge component is insignificant if one uses a fast or ultra-
fast recovery bootstrap diode. Ultra-fast recovery diodes are
recommended (see the Bill of Material included in the
Appendix).
The upper bias supply operating current will vary with PWM
duty-cycle. The upper bias current is typically 1.1mA when
driving a 1000pF load with a 50kHz switching voltage
waveform (at a 50% duty-cycle). This value represents the
sum of all three of the previously discussed components of
current. Figure 14 of the HIP4082 datasheet [1] shows typical
full bridge level-shift current as a function of switching
frequency (at a 50% duty-cycle). As duty-cycle decreases, the
level-shift current increases somewhat. The best way to
determine the exact level of current is to measure it at the
duty-cycle desired. In many applications, the duty-cycle is
constantly changing with time. Therefore a 50% duty-cycle
waveform is a good choice for purposes of determining
bootstrap average current requirements.
The level-shift current also tends to increase with frequency,
because the leading edge of each level-shift signal
incorporates a robust current pulse to guarantee that the
translation pulse is not interrupted by stray IC currents
induced by the high dv/dt levels which occur during
switching. Figure 14 of the HIP4082 data sheet includes this
effect also.
Bootstrap Supply Design
The bootstrap supply technique is a simple, cost-effective
way to power the upper MOSFET’s gate and provide bias
supply to the floating logic sections of the HIP4082. Only two
components per bridge phase are needed to implement the
bootstrap supply. For a full bridge driver such as the
HIP4082, diodes D
1
and D
2
, and capacitors C
1
and C
2
are
all that is needed to provide this function as shown in the
schematic in the Appendix.
The bootstrap capacitor gets charged or “refreshed” using
the low voltage (V
CC
) bias supply. A fast recovery diode is
connected between the bootstrap capacitor and V
CC
, with
the anode going to V
CC
and the cathode to the capacitor.
The other side of the capacitor is tied to COM or V
SS
potential through a low-side power MOSFET throughout the
period during which the low-side MOSFET or its body diode
is conductive. Since the body diode conduction depends on
some remaining load current at the time that an upper
MOSFET is turned off, it is generally wise to reserve a short
period during every PWM cycle to turn on the lower
MOSFET, thereby guaranteeing that refresh occurs.
The refresh time allotted must last long enough to replace all
of the charge that is sucked out of the bootstrap capacitor
during the time since the last refresh period ended. There
are 3 components of charge which must be replaced. The
least significant is that due to the bias supply needs of the
upper logic section of the HIP4082, which typically will be
145µA when the MOSFET is gated on and about 1.5mA
when it is gated off. Bootstrap diode leakage current will
normally be negligible, but should be investigated. The
required charge is the upper bias supply current of the
HIP4082 integrated over one PWM period.
The second component, usually very significant, is the charge
required to pump up the equivalent MOSFET input
capacitance to the V
CC
level. The charge, Q
GATE
, is equal to
the product of the equivalent gate capacitance, C
GATE
, and
the magnitude of gate voltage applied, V
CC
. The power
dissipated in pumping this charge is the product of the charge,
Q
GATE
, the applied voltage, V
CC
, and the frequency of
application, f
PWM
. Most MOSFET data sheets supply values
3
Special Concerns
When the HIP4082 IC first powers up, there is a 400ns to
500ns pulse applied to both lower MOSFET gates which
serves to charge the bootstrap capacitors for the first time.
This action corresponds with a simultaneous off pulse to
both upper MOSFETs through the level-shift circuitry. If it is
necessary to completely charge the bootstrap capacitors
upon power-up, then this pulse imposes limitations on the
size allowed for the bootstrap capacitors. If too large, they
may not get charged within the 400ns to 500ns window. The
start-up pulses are sent regardless of what state the input
logic signals (except for DIS) are in at the time.
In the event that MOSFETs are used with very large Gate-
Source input capacitances (or when several smaller
MOSFETs are paralleled) complete charging of the
bootstrap capacitors can be guaranteed by issuing lower
MOSFET turn-on pulses of a longer duration than the default
duration issued by the HIP4082. The peak current drawn
from the V
CC
supply can be quite severe in the case of a
1.0µF bootstrap capacitor, for example. In this example, it
would take 24A to charge the capacitor in 0.5µs. Obviously
the bootstrap diode equivalent series resistance, coupled
Application Note 9611
with the additional trace impedances in the bootstrap
charging loop will not allow 24A to flow. Often the customer’s
power supply used for biasing the driver and control logic is
incapable of supplying this magnitude of current. For this
reason, much larger bypass capacitors are recommended
for the V
CC
supply than are used for the bootstrap
capacitors. A good rule of thumb is ten times greater. In the
example above, if the bootstrap circuit impedance is
estimated to be about 5Ω, then the peak current will be only
2.4A. The time required to charge up the bootstrap capacitor
(an exponential charge characteristic is assumed) to just
under 11V will be approximately 12µs. (24 times the charge
time allotted by default within the IC!) To avoid problems
when driving large MOSFETs or when paralleling MOSFETs
it is necessary to consider the low voltage bias supply’s
output impedance, the bias supply’s bypass capacitor
(located at the HIP4082 IC), the size of the bootstrap
capacitor (it should also be about 10 times the equivalent
input capacitance of the connected MOSFETs), and the
forward resistance characteristic of the chosen bootstrap
diode.
In order to minimize transformer size and maximize winding
fill, the primary was formed of 3 separate windings which were
paralleled to supply the approximately 30A
RMS
required at
rated output power. Each primary winding’s DC resistance is
less than 10mΩ. There are two equal, but separate,
secondary power output windings. When series-connected,
these secondary power output windings provide 230V
AC
load
power. The US configured eval-boards are provided with
paralleled output windings for 115V
AC
operation. Series
connection via soldered jumper wires allows for 230V
AC
operation, but this shouldn’t be attempted without changing
the power MOSFETs and the voltage ratings of several
capacitors. A 500V MOSFET with an r
DS(ON)
of 1.5Ω such as
the Intersil IRF830R would be a suitable device for 230V
AC
operation. Besides having to double the capacitor voltage
ratings of C
23
, C
27
and C
13
, the capacity of C
23
and C
27
will
have to be dropped by a factor of 4. This maintains the power
dissipation in resistors, R
34
and R
38
to remain as they are for
the 115V
AC
design.
A third secondary winding provides low voltage control
power to all of the secondary-side inverter logic and gate
drivers. This voltage is nominally 20.5V (peak of the square-
wave) when there is a nominal 13.6V
DC
applied to the
battery input terminals of the eval-board. This winding must
output at least 14V at the minimum battery voltage in order
to keep the series regulator out of saturation. This winding
carries less than 100mA, so winding gauge will be
determined more for strength than for current carrying
capacity.
Transformer Specification
Current Product-to-Market needs often require having a
magnetics supplier design the magnetics devices in your
design. We followed this approach with respect to the eval-
board’s transformer and choke. The electronics designer
provides a detailed specification to the transformer supplier.
The specification should include the minimum frequency of
operation, the maximum applied voltage and waveform, the
continuous and overload current profiles, and operating
ambient temperature. Required transformer regulation must
also be specified. The transformer designer needs to know
this in order to size the transformer wire and leakage
inductance. The power handling capability and operating
frequency influences choice of core size and geometry and
ultimately the cost and size of the transformer. (Refer to the
Bill of Material included in the Appendix for information
regarding the transformer.)
It is important that the transformer designer have knowledge
of the transformer excitation waveform. The reason that this
is important is that the current waveshape dictates the form
factor or the value of RMS (root-mean-square) current that
will result for a given required average current. The size of
the filter capacitor, the equivalent series impedance of the
secondary, and the output voltage waveshape will determine
the current waveform and form factor. The RMS current
determines the power losses in the transformer and
temperature rise. To minimize ringing on the inverter bridge
of the primary inverter it will help to minimize the leakage
inductance of the transformer. For the DC-to-AC inverter
eval-board, power ferrite material, E core style PQ3230, was
used for the core.
Secondary Inverter Design
The secondary-side inverter and control is designed to
provide a near constant 115V
AC
to 120V
AC
, 55Hz output
voltage waveform. The inverter can supply approximately
120W to loads such as small fans, lights, radios and other
small electric appliances that might be handy to have with
you on a camping trip, for example.
In addition, a simple current trip circuit and an overtemp
limiter was incorporated in order to provide features similar
to a commercially available DC-to-AC inverter of similar
rating and purpose.
The secondary-side inverter includes the following functions:
• A high voltage input rectifier and filter
• A high voltage DC-to-AC inverter and control circuits,
providing over-current, thermal protection, and output
voltage regulation to compensate for widely varying
battery voltages and output current;
• A neon lamp to warn of the presence of high voltage and
ELECTRICAL SHOCK HAZARD.
Details of these circuits
follow.
Input Filter and Rectifiers
There are two full wave rectifiers. One rectifies the 162V
secondary voltage to provide the DC high voltage bus for the
4
Application Note 9611
inverter. Ultra-fast recovery, 3A rectifiers (UF5405), rectify
the 60kHz square-wave voltage waveform. Ultra-fast
recovery rectifiers reduce the recovery energy dissipated.
Even ultrafast diodes, such as the UF5405, forced a slight
reduction in the predicted output power rating of the inverter
due to higher than expected recovery energy loss. Addition
of some series impedance between the filter capacitor, C
8
,
and the rectifier bridge, possibly even relocation of the shunt
resistor, R
23
, would help to reduce this power. Users should
keep this in mind when designing their own solutions.
The choice of square-wave excitation waveform allows a
smaller rectifier filter capacitor to be used, while still
maintaining very low high voltage DC bus ripple.
The second rectifier provides control power to the linear
regulator, which in turn provides regulated 12V
DC
for all
secondary-side control and gate drivers. This voltage varies
from 15V to 23V as the battery voltage varies from 10V to
15V. A second, isolated winding from the transformer excites
this rectifier. Unlike the high voltage rectifier, this rectifier
bridge incorporates 1Ω of series resistance, R
35
, and a
relatively small filter capacitor, C
9
. No significant heating
occurred in the 1A UF4002 rectifiers. Filter ripple is controlled
by the linear regulator, U
3
, input (test point TP6). The low
current linear regulator provides 12V bias for all of the
secondary-side control, driver ICs, and for MOSFET gate
drive.
CH1 = 50V
M = 2.5µs
GLITCH CH1
MOSFET power dissipation. Figure 3 shows the actual
output voltage waveform.
1
FIGURE 3. SECONDARY-SIDE BRIDGE OUTPUT
Varying the width of the positive and negative conduction
periods inversely with the voltage level of the high voltage
bus maintains the RMS value of the output waveform
relatively constant.
Phase shifting two nearly perfect square-waves from the left
and right half-bridges making up the inverter produces the
waveforms shown in Figure 3. The left half-bridge includes
MOSFETs Q
6
and Q
8
and the right half-bridge includes
MOSFETs Q
7
and Q
9
. The waveforms generated at the
common connections (sometimes referred to as the phase
node or phase terminal) of the MOSFET half-bridges appear
as shown in Figure 4.
Trace 1 is the voltage at the phase node of Q
6
and Q
8
and
Trace 2 is the voltage at the phase node of Q
7
and Q
9
. The
vector difference between the two phase node voltages is
the output voltage shown in Figure 3.
The required phase-shift function is implemented by a simple
control circuit. The technique can be expanded to create
sinusoidal or other output waveform types with added
complexity, of course. The control circuits used in this design
will be discussed in the section, “Secondary Inverter Control
Circuits.”
The high voltage output waveform can exhibit a nasty
voltage transient, with the potential to mess up the output
voltage across the connected load and to possibly destroy
the high voltage gate driver, HIP2500, or the secondary-side
inverter MOSFETs. Therefore phase-to-phase and DC bus
snubbers were added. Resistor, R
34
and capacitor, C
23
,
implement the bus snubber and resistor, R
38
and capacitor,
C
27
, comprise the phase-to-phase snubber. Phase-to-phase
or “AC” snubbers allow their capacitors to completely charge
and discharge each cycle of the switching waveform and at
high switching frequencies will dissipate a lot of power. R
38
and C
27
were not used, but space for them was provided.
Secondary-Side Inverter
The secondary-side inverter functions include the power
MOSFETs Q
6
through Q
9
, their associated gate resistors
and capacitors, the snubber, the current-sensing resistor, the
output choke, the indicator lamp and the filter.
The inverter topology is a full-wave H-bridge and synthesizes
a pseudo sin-wave by alternately switching on Q
6
and Q
9
for
positive half sin-waves and Q
7
and Q
8
for negative half sine-
waves. Since the inverter requires the ability to regulate the
RMS output voltage over a wide ranging DC battery input
voltage, some means of varying the conduction period of the
Q
6
-Q
9
and Q
7
-Q
8
pairs must be implemented.
The choice of square-wave output over sine-wave output
simplified the pulse-width-modulator (PWM) and minimized
5
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