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SIT3521AE-2C128-7S340.000000Y

产品描述LVDS Output Clock Oscillator, 340MHz Nom, QFN, 10 PIN
产品类别无源元件    振荡器   
文件大小1MB,共45页
制造商SiTime
标准
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SIT3521AE-2C128-7S340.000000Y概述

LVDS Output Clock Oscillator, 340MHz Nom, QFN, 10 PIN

SIT3521AE-2C128-7S340.000000Y规格参数

参数名称属性值
是否Rohs认证符合
Objectid145145419382
包装说明LCC10,.12X.2,50/40
Reach Compliance Codeunknown
Country Of OriginMalaysia, Taiwan, Thailand
YTEOL6.8
最长下降时间0.47 ns
频率调整-机械NO
频率稳定性20%
JESD-609代码e4
安装特点SURFACE MOUNT
端子数量10
标称工作频率340 MHz
最高工作温度105 °C
最低工作温度-40 °C
振荡器类型LVDS
输出负载100 OHM
封装等效代码LCC10,.12X.2,50/40
物理尺寸5.0mm x 3.2mm x 0.9mm
最长上升时间0.47 ns
最大供电电压3.08 V
最小供电电压2.52 V
标称供电电压2.8 V
表面贴装YES
最大对称度55/45 %
端子面层Nickel/Palladium/Gold (Ni/Pd/Au)

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SiT3521
1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator
Description
The
SiT3521
is an ultra-low jitter, user programmable
oscillator which offers the system designer great flexibility
and functionality.
The device supports two in-system programming options
after powering up at a default, factory programmed startup
frequency:
Features
Any-frequency mode where the clock output can be
re-programmed to any frequency between 1 MHz and
340 MHz in 1 Hz steps
Digitally controlled oscillator (DCO) mode where the clock
output can be steered or pulled by up to ±3200 ppm with
5 to 94 ppt (parts per trillion) resolution.
The device’s default start-up frequency is specified in the
ordering code. User programming of the device is achieved
via I
2
C or SPI. Up to 16 I
2
C addresses can be specified by
the user either as a factory programmable option or via
hardware pins, enabling the device to share the I
2
C with
other I
2
C devices.
The SiT3521 utilizes SiTime’s unique DualMEMS
®
temperature sensing and TurboCompensation
®
technology
to deliver exceptional dynamic performance:
Programmable frequencies (factory or via I
2
C/SPI)
from 1 MHz to 340 MHz
Digital frequency pulling (DCO) via I
2
C/SPI
Output frequency pulling with perfect pull linearity
13 programmable pull range options to
±3200
ppm
Frequency pull resolution as low as 5 ppt (0.005 ppb)
0.21 ps typical integrated phase jitter (12 kHz to 20 MHz)
Integrated LDO for on-chip power supply noise filtering
0.02 ps/mV PSNR
-40°C to 105°C operating temperature
LVPECL, LVDS, or HCSL outputs
Programmable LVPECL, LVDS Swing
LVDS Common Mode Voltage Control
RoHS and REACH compliant, Pb-free, Halogen-free
and Antimony-free
Applications
Resistant to airflow and thermal shock
Resistant to shock and vibration
Superior power supply noise rejection
Combined with wide frequency range and user
programmability, this device is ideal for telecom, networking
and industrial applications that require a variety of
frequencies and operate in noisy environment.
Ethernet: 1/10/40/100/400 Gbps
G.fast and xDSL
Optical Transport: SONET/SDH, OTN
Clock and data recovery
Processor over-clocking
Low jitter clock generation
Server, storage, datacenter
Test and measurement
Broadcasting
Block Diagram
Package Pinout
(10-Lead QFN, 5.0 x 3.2 mm)
SD
SC
A/
M
LK ISO
10
9
OE / NC
OE / NC
GND
1
8
VDD
OUT-
OUT+
2
7
3
4
5
6
A1 A0
/N /N
C/ C/
M SS
O
SI
Figure 1. SiT3521 Block Diagram
Figure 2. Pin Assignments (Top view)
(Refer to
Table 14
for Pin Descriptions)
Rev 1.01
30 April 2021
www.sitime.com
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