Si5100
SiPHY
®
OC-48/STM-16 SONET/SDH T
RANSCEIVER
Features
Complete, low-power, high-speed, SONET/SDH transceiver with
integrated limiting amp, CDR, CMU, and MUX/DEMUX
Data rates supported:
SONET-compliant loop timed
OC-48/STM-16 through 2.7 Gbps
operation
FEC
Programmable slicing level and
sample phase adjustment
Low-power operation 1.2 W (typ)
DSPLL based clock multiplier
LVDS/LVPECL compatible
interface
unit w/ selectable loop filter
Single supply 1.8 V operation
bandwidths
15 x 15 mm BGA package
Integrated limiting amplifier
Loss-of-signal (LOS) alarm
Diagnostic and line loopbacks
Si5100
Bottom View
Ordering Information:
See page 35.
Applications
SONET/SDH transmission
systems
Optical transceiver modules
SONET/SDH test equipment
Description
The Si5100 is a complete low-power transceiver for high-speed serial
communication systems operating between OC-48 and 2.7 Gbps. The receive
path consists of a fully-integrated limiting amplifier, clock and data recovery unit
(CDR), and 1:16 deserializer. The transmit path combines a low-jitter clock
multiplier unit (CMU) with a 16:1 serializer. The CMU uses Silicon Laboratories’
DSPLL technology to provide superior jitter performance while reducing design
complexity by eliminating external loop filter components. To simplify BER
optimization in long-haul applications, programmable slicing and sample phase
adjustment are supported. The Si5100 operates from a single 1.8 V supply over
the industrial temperature range (–20 to 85 °C).
Functional Block Diagram
SLICELVL
PHASEADJ
1:16
DEMUX
RXDIN
RXDOUT[15:0]
Diagnostic
Loopback
RXCLK
÷
Limiting
AMP
CDR
Line
Loopback
16:1
MUX
TXDOUT
TXDIN[15:0]
TXCLKOUT
M
DSPLL
T
TX CMU
TXCLK16IN
REFCLK
BWSEL[1:0]
Rev. 1.5 11/12
Copyright © 2012 by Silicon Laboratories
Si5100
Si5100
T
ABLE
Section
OF
C
ONTENTS
Page
1. Si5100 Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3. Si5100 Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5. Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1. Receiver Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2. Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5.3. Clock and Data Recovery (CDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.4. Deserialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5. Voltage Reference Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.6. Auxiliary Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.7. Receive Data Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6. Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1. DSPLL
®
Clock Multiplier Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2. Serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
7. Loop Timed Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
8. Diagnostic Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9. Line Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
11. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
12. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
13. Transmit Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
14. Internal Pullups and Pulldowns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
15. Power Supply Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
16. Si5100 Pinout: 195 BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
17. Pin Descriptions: Si5100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
18. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
19. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
20. 15x15 mm 195L PBGA Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Rev. 1.5
3
Si5100
1. Si5100 Detailed Block Diagram
SLICEMODE
SLICELVL
PHASEADJ
LTR
RXLOL
RXMSBSEL
RXSQLCH
DLBK
LOS
RXDIN
Lim iting
Amp
CDR
1:16
DE-
MUX
32:16
MUX
RXDOUT[15:0]
LOSLVL
LOS
RXAMPMON
RXCLK1DSBL
RXCLK1
FIFOERR
FIFORST
RXCLK2
RXCLK2DSBL
RXCLK2DIV
TXSQLCH
TXDOUT
16:1
MUX
FIFO
32:16
MUX
TXDIN[15:0]
TXCLKDSBL
TXCLKOUT
TXCLK16OUT
TXCLK16IN
TXLOL
CMU
REFCLK
TXMSBSEL
BWSEL[1:0]
REFRA TE
LPTM LLBK
REFSEL
LLBK
4
Rev. 1.5
Si5100
2. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature
LVTTL Output Supply Voltage
Si5100 Supply Voltage
Symbol
T
A
V
DDIO
VDD
Test Condition
Min
*
–20
1.71
1.71
Typ
25
—
1.8
Max
*
85
3.47
1.89
Unit
°C
V
V
*Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated.
V
SIGNAL+
Differential
V
ICM
, V
OCM
SIGNAL–
I/Os
0V
(SIGNAL+) – (SIGNAL–)
Differential
Voltage Swing
V
V
ID
,V
OD
(V
ID
= 2 V
ISE
)
Differential Peak-to-Peak Voltage
t
V
I
V
ISE
, V
OSE
Single Ended Voltage
Figure 1. Differential Voltage Measurement
(RXDIN, RXDOUT, RXCLK1, RXCLK2, TXDIN, TXDOUT, TXCLKOUT, TXCLK16OUT, TXCLK16IN)
t
cd
TXDOUT,
TXDIN
t
CP
t
CH
TXCLKOUT,
TXCLK16IN
RXDOUT
RXCLK1
t
cq1
t
cq2
Figure 2. Data to Clock Delay
Rev. 1.5
5
微控制器 MCU
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