Nuvoton 8-bit 8051-based Microcontroller
N78E366A
Data Sheet
N78E366A Data Sheet
CONTENTS
1. DESCRIPTION .................................................................................................................................................. 4
2. FEATURES ....................................................................................................................................................... 5
3. BLOCK DIAGRAM ............................................................................................................................................ 7
4. PIN CONFIGURATIONS ................................................................................................................................... 8
5. MEMORY ORGANIZATION ............................................................................................................................ 14
5.1 Internal Program Memory ................................................................................................................. 14
5.2 External Program Memory ................................................................................................................ 16
5.3 Internal Data Memory ....................................................................................................................... 17
5.4 On-chip XRAM .................................................................................................................................. 19
5.5 External Data Memory ...................................................................................................................... 19
6. SPECIAL FUNCTION REGISTER (SFR) ....................................................................................................... 21
7. GENERAL 80C51 SYSTME CONTROL ......................................................................................................... 24
8. AUXILIARY RAM (XRAM) ............................................................................................................................... 28
9. I/O PORT STRUCTURE AND OPERATION .................................................................................................. 30
10. TIMERS/COUNTERS.................................................................................................................................... 34
10.1 Timer/Counters 0 and 1 .................................................................................................................. 34
10.1.1 Mode 0 (13-bit Timer) ...................................................................................................... 36
10.1.2 Mode 1 (16-bit Timer) ...................................................................................................... 37
10.1.3 Mode 2 (8-bit Auto-reload Timer) .................................................................................... 37
10.1.4 Mode 3 (Two Separate 8-bit Timers) ............................................................................... 38
10.2 Timer/Counter 2 .............................................................................................................................. 39
10.2.1 Capture Mode .................................................................................................................. 42
10.2.2 Auto-reload Mode ............................................................................................................ 42
10.2.3 Baud Rate Generator Mode ............................................................................................ 43
10.2.4 Clock-out Mode................................................................................................................ 44
11. WATCHDOG TIMER ..................................................................................................................................... 45
11.1 Function Description of Watchdog Timer ........................................................................................ 45
11.2 Applications of Watchdog Timer ..................................................................................................... 47
12. POWER DOWN WAKING-UP TIMER .......................................................................................................... 48
12.1 Function Description of Power Down Waking-up Timer ................................................................. 48
12.2 Applications of Power Down Waking-up Timer............................................................................... 49
13. SERIAL PORT ............................................................................................................................................... 51
13.1 Mode 0 ............................................................................................................................................ 53
13.2 Mode 1 ............................................................................................................................................ 55
13.3 Mode 2 ............................................................................................................................................ 57
13.4 Mode 3 ............................................................................................................................................ 59
13.5 Baud Rate ....................................................................................................................................... 61
13.6 Multiprocessor Communication....................................................................................................... 62
14. SERIAL PERIPHERAL INTERFACE (SPI) ................................................................................................... 64
14.1 Features .......................................................................................................................................... 64
14.2 Function Description ....................................................................................................................... 64
14.3 Control Registers of SPI ................................................................................................................. 67
14.4 Operating Modes ............................................................................................................................ 69
14.4.1 Master mode .................................................................................................................... 69
14.4.2 Slave Mode ...................................................................................................................... 69
14.5 Clock Formats and Data Transfer ................................................................................................... 70
14.6 Slave Select Pin Configuration ....................................................................................................... 72
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Publication Release Date: March 11, 2011
Revision: V2.0
14.7 Mode Fault Detection ...................................................................................................................... 73
14.8 Write Collision Error ........................................................................................................................ 73
14.9 Overrun Error .................................................................................................................................. 73
14.10 SPI Interrupts ................................................................................................................................ 74
15. PULSE WIDTH MODULATOR (PWM) ......................................................................................................... 75
16. TIMED ACCESS PROTECTION (TA)........................................................................................................... 79
17. INTERRUPT SYSTEM .................................................................................................................................. 81
17.1 Priority Level Structure .................................................................................................................... 87
17.2 Interrupt Latency ............................................................................................................................. 89
18. IN SYSTEM PROGRAMMING (ISP) ............................................................................................................. 90
18.1 ISP Procedure ................................................................................................................................. 90
18.2 ISP Commands ............................................................................................................................... 93
18.3 User Guide of ISP ........................................................................................................................... 93
18.4 ISP Demo Codes ............................................................................................................................ 94
19. POWER SAVING MODES ............................................................................................................................ 98
19.1 Idle Mode ........................................................................................................................................ 98
19.2 Power Down Mode .......................................................................................................................... 99
20. CLOCK SYSTEM ........................................................................................................................................ 100
20.1 12T/6T mode ................................................................................................................................. 100
20.2 External Clock Source .................................................................................................................. 102
20.3 On-chip RC Oscillator ................................................................................................................... 102
21. POWER MONITORING .............................................................................................................................. 103
21.1 Power-on Detection ...................................................................................................................... 103
21.2 Brown-out Detection ..................................................................................................................... 103
22. RESET CONDITIONS ................................................................................................................................. 107
22.1 Power-on Reset ............................................................................................................................ 108
22.2 Brown-out Reset ........................................................................................................................... 108
22.3 RST Pin Reset .............................................................................................................................. 108
22.4 Watchdog Timer Reset ................................................................................................................. 109
22.5 Software Reset.............................................................................................................................. 109
22.6 Boot Select .................................................................................................................................... 110
22.7 Reset State ................................................................................................................................... 111
23. AUXILIARY FEATURES ............................................................................................................................. 113
24. CONFIG BYTES .......................................................................................................................................... 114
25. INSTRUCTION SET .................................................................................................................................... 117
26. ELECTRICAL CHARACTERISTICS ........................................................................................................... 121
26.1 Absolute Maximum Ratings .......................................................................................................... 121
26.2 DC Electrical Characteristics ........................................................................................................ 121
26.3 AC Electrical Characteristics ......................................................................................................... 127
27. PACKAGES ................................................................................................................................................. 131
28. DOCUMENT REVISION HISTORY ............................................................................................................ 135
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Publication Release Date: March 11, 2011
Revision: V2.0
N78E366A Data Sheet
1. DESCRIPTION
N78E366A is an 8-bit microcontroller, which has an in-system programmable Flash supported. The instruction
set of N78E366A is fully compatible with the standard 8051. N78E366A contains a 64k bytes of main Flash
APROM, in which the contents of the main program code can be updated by parallel Programmer/Writer or In
System Programming (ISP) method which enables on-chip firmware updating. There is an additional 2.5k bytes
called LDROM for ISP function. N78E366A provides 256 bytes of SRAM, 1k bytes of auxiliary RAM (XRAM),
four 8-bit bi-directional and bit-addressable I/O ports, an additional 8-bit bi-directional and bit-addressable port
P4 for LQPF-48 package (PLCC-44 and PQFP-44 just have low nibble 4 bits of P4 and DIP-40 does not have
this additional P4), three 16-bit Timers/Counters, one UART, five PWM output channels, and one SPI. These
peripherals equip with 11-source with 4-level priority interrupts capability. To facilitate programming and verifi-
cation, the Flash inside the N78E366A allows the Program Memory to be programmed and read electronically.
Once the code confirms, the user can lock the code for security.
N78E366A is built in a precise on-chip RC oscillator of 22.1184MHz/11.0592MHz selected by CONFIG setting,
factory trimmed to ±1% at room temperature. N78E366A provides additional power monitoring detection such
as power-on and Brown-out detection. It stabilizes the power-on/off sequence for a high reliability system de-
sign.
N78E366A microcontroller operation consumes a very low power. Two economic power modes to reduce pow-
er consumption, Idle mode and Power Down mode. Both of them are software selectable. The Idle mode turns
off the CPU clock but allows continuing peripheral operation. The Power Down mode stops the whole system
clock for minimum power consumption.
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Publication Release Date: March 11, 2011
Revision: V2.0
2. FEATURES
Fully static design 8-bit CMOS microcontroller.
Wide supply voltage of 2.4V to 5.5V and wide frequency from 4MHz to 40MHz.
12T mode compatible with the tradition 8051 timing.
6T mode supported for double performance.
On-chip RC oscillator of 22.1184MHz/11.0592MHz, trimmed to ±1% at room temperature for the precise
system clock.
64k bytes Flash APROM for the application program.
2.5k bytes Flash LDROM for ISP code.
In-System-Programmable (ISP) built in. ISP Erasing or programming supports wide operating voltage
3.0V~5.5V.
Flash 10,000 writing cycle endurance. Greater than 10 years data retention under 85℃.
256 bytes of on-chip RAM.
1k bytes of on-chip auxiliary RAM (XRAM).
64k bytes Program Memory address space and 64k bytes Data Memory address space.
Maximum five 8-bit general purpose I/O ports pin-to-pin compatible with standard 8051, additional
INT2
and
INT3
on packages except DIP-40.
Three 16-bit Timers/Counters.
One dedicate timer for Power Down mode waking-up.
One full-duplex UART port.
Five pulse width modulated (PWM) output channels.
One SPI communication port.
11-source, 4-priority-level interrupts capability.
Programmable Watchdog Timer.
Power-on reset.
Brown-out detection interrupt and reset, 4-level selected.
Supports software reset function.
Built-in power management with Idle mode and Power Down mode.
Code lock for data security.
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Publication Release Date: March 11, 2011
Revision: V2.0
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