PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I-04
F
EMTO
C
LOCKS
™C
RYSTAL
/LVCMOS-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
F
EATURES
• Four LVDS outputs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following applications: SONET/SDH, SATA,
or 10Gb Ethernet
• Output frequency range: 140MHz - 170MHz,
560MHz - 680MHz
• VCO range: 560MHz - 680MHz
• Crystal oscillator and CLK range: 17.5MHz - 21.25MHz
• RMS phase jitter @ 622.08MHz output, using a 19.44MHz
crystal (12kHz - 20MHz): 0.71ps (typical)
• RMS phase jitter @ 156.25MHz output, using a 19.53125MHz
crystal (1.875MHz - 20MHz): 0.51ps (typical)
• RMS phase jitter @ 155.52MHz output, using a 19.44MHz
crystal (12kHz - 5MHz): 0.75ps (typical)
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS844004I-04 is a 4 output LVDS
Synthesizer optimized to generate clock
HiPerClockS™
frequencies for a variety of high performance
applications and is a member of the
HiPerClocks
TM
family of high perfor mance
clock solutions from ICS. This device can select its input
reference clock from either a crystal input or a single-
ended clock signal. It can be configured to generate 4
outputs with individually selectable divide-by-one or
divide-by-four function via the 4 frequency select pins
(F_SEL[3:0]). The ICS844004I-04 uses ICS’ 3
rd
generation
low phase noise VCO technology and can achieve 1ps
or lower typical rms phase jitter. This ensures that it
will easily meet clocking requirements for SDH (STM-1/
STM-4/STM-16) and SONET (OC-3/OC12/OC-48). This
device is suitable for multi-rate and multiple por t line
card applications. The ICS844004I-04 is conveniently
packaged in a small 24-pin TSSOP package.
IC
S
B
LOCK
D
IAGRAM
XTAL_IN
P
IN
A
SSIGNMENT
÷1
Phase
Detector
VCO
÷4
0
1
OSC
XTAL_OUT
CLK
Pulldown
INPUT_SEL
Pulldown
0
Q0
nQ0
1
M = ÷32
MR
Pulldown
F_SEL0
Pullup
0
1
Q1
nQ1
nQ1
Q1
V
DD
o
Q0
nQ0
MR
F_SEL3
nc
V
DDA
F_SEL0
V
DD
F_SEL1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
nQ2
Q2
V
DDO
Q3
nQ3
GND
F_SEL2
INPUT_SEL
CLK
GND
XTAL_IN
XTAL_OUT
F_SEL1
Pullup
0
1
ICS844004I-04
Q2
nQ2
F_SEL2
Pullup
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
0
1
Q3
nQ3
F_SEL3
Pullup
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844004AGI-04
www.icst.com/products/hiperclocks.html
1
REV. A
FEBRUARY
25, 2009
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I-04
F
EMTO
C
LOCKS
™C
RYSTAL
/LVCMOS-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
Type
Description
Differential output pair. LVDS interface levels.
Output supply pins.
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inver ted outputs nQx
Pulldown
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
Pullup
Frequency select pins. LVCMOS/LVTTL interface levels. See Table 3.
No connect.
Analog supply pin.
Core supply pin.
Parallel resonant cr ystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Power supply ground.
Pulldown LVCMOS/LVTTL clock input.
Selects between cr ystal or CLK inputs as the the PLL Reference source.
Pulldown Selects XTAL inputs when LOW. Selects CLK when HIGH.
LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 22
4, 5
6
7,
10,
12,
18
8
9
11
13, 14
1 5, 19
16
17
20, 21
23, 24
Name
nQ1, Q1
V
DDO
Q0, nQ0
MR
F_SEL3,
F_SEL0,
F_SEL1,
F_SEL2
nc
V
DDA
V
DD
XTAL_OUT,
XTAL_IN
GND
CL K
INPUT_SEL
nQ3, Q3
Q2, nQ2
Output
Power
Ouput
Input
Input
Unused
Power
Power
Input
Power
Input
Input
Output
Output
NOTE:
Pulldown and Pullup
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3. O
UTPUT
C
ONFIGURATION
Inputs
F_SELx
0
1
0
1
0
1
0
1
XTAL (MHz)
19.44
19.44
18.75
18.75
19.53125
19.53125
20.141601
20.141601
AND
F
REQUENCY
R
ANGE
F
UNCTION
T
ABLE
N Divider Value
N0:N3
1
4
1
4
1
4
1
4
Output Frequency (MHz)
Q0/nQ0:Q3/nQ3
622.08
155.52
600
150
625
156.25
644.5312
161.13
Application
SONET/SDH
SATA
10 Gigabit Ethernet
10 Gigabit Ethernet
66B/64B FEC
VCO
(MHz)
622.08
622.08
60 0
600
625
625
644.5312
644.5312
844004AGI-04
www.icst.com/products/hiperclocks.html
2
REV. A FEBRUARY 25, 2009
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I-04
F
EMTO
C
LOCKS
™C
RYSTAL
/LVCMOS-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
4.6V
-0.5V to V
CC
+ 0.5V
10mA
15mA
70°C/W (0 mps)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, TA = -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
80
8
87
Maximum
3.465
3.465
3.465
Units
V
V
V
mA
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, TA = -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
CLK,
MR, INPUT_SEL
F_SEL0:F_SEL3
I
IL
Δ
V/
ΔT
Input Low Current
Input Edge Rate
CLK,
MR, INPUT_SEL
F_SEL0:F_SEL3
CLK
V
DD
= V
IN
= 3.465
V
DD
= V
IN
= 3.465
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
20% - 80%
-5
-150
TB D
Test Conditions
Minimum Typical
2
-0.3
Maximum
V
DD
+ 0.3
0.8
15 0
5
Units
V
V
µA
µA
µA
µA
V/ns
T
ABLE
4C. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, TA = -40°C
TO
85°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
Minimum
Typical
350
40
1.35
50
Maximum
Units
mV
mV
V
mV
844004AGI-04
www.icst.com/products/hiperclocks.html
3
REV. A FEBRUARY 25, 2009
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I-04
F
EMTO
C
LOCKS
™C
RYSTAL
/LVCMOS-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
Test Conditions
Minimum
17.5
Typical
Maximum
21.25
50
7
1
Units
MHz
Ω
pF
mW
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant crystal.
Fundamental
T
ABLE
6. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, TA = -40°C
TO
85°C
Symbol
f
OUT
t
sk(o)
Parameter
Output Frequency
Output Skew; NOTE 1, 2
155.52MHz,
Integration Range: 12kHz - 20MHz
156.25MHz,
Integration Range: 1.875MHz - 20MHz
622.08MHz,
Integration Range: 12kHz - 20MHz
20% to 80%
Test Conditions
Output Divider = ÷1
Output Divider = ÷4
Minimum
560
140
TBD
0.75
0.51
0.71
29 0
Typical
Maximum
680
170
Units
MHz
MH z
ps
ps
ps
ps
ps
%
t
jit(Ø)
RMS Phase Jitter (Random);
NOTE 3
t
R
/ t
F
Output Rise/Fall Time
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
844004AGI-04
www.icst.com/products/hiperclocks.html
4
REV. A FEBRUARY 25, 2009
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I-04
F
EMTO
C
LOCKS
™C
RYSTAL
/LVCMOS-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
T
YPICAL
P
HASE
N
OISE AT
155.52MH
Z
A
T
3.3V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
➤
OC3 SONET Filter
155.52MHz
RMS Phase Jitter (Random)
12kHz to 5MHz = 0.75ps (typical)
N
OISE
P
OWER
dBc
Hz
Raw Phase Noise Data
➤
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
100
➤
1k
Phase Noise Result by adding
OC3 SONET Filter to raw data
10k
100k
1M
10M
100M
O
FFSET
F
REQUENCY
(H
Z
)
T
YPICAL
P
HASE
N
OISE AT
622.08MH
Z
A
T
3.3V
0
-10
-20
-30
-40
-50
-60
➤
OC 12 SONET Filter
622.08MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.71ps (typical)
N
OISE
P
OWER
dBc
Hz
-70
-80
-90
-100
-110
-120
-140
-150
-160
-170
-180
-190
10
100
1k
10k
Raw Phase Noise Data
➤
➤
Phase Noise Result by adding
OC 12 SONET Filter to raw data
-130
100k
1M
10M
100M
O
FFSET
F
REQUENCY
(H
Z
)
844004AGI-04
www.icst.com/products/hiperclocks.html
5
REV. A FEBRUARY 25, 2009
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