IDTCV149
PROGRAMMABLE FLEXPC™ CLOCK FOR AMD K8 PROCESSOR ATI RS480
COMMERCIAL TEMPERATURE RANGE
PROGRAMMABLE FLEXPC™
CLOCK FOR AMD K8
PROCESSOR ATI RS480
FEATURES:
• One high precision N and SSC programmable PLL for CPU
• One high precision N and SSC programmable PLL for SRC[2:1]
• One high precision N and SSC programmable PLL for SRC0
[7:3] (PCI Express)
• One high precision PLL for 48MHz
• Band-gap circuit for differential outputs
• Support multiple spread spectrum modulation, down and
center
• Support SMBus block read/write, index read/write
• Selectable output strength for REF, PCI, 48MHz, HTT66
• Available in SSOP and TSSOP packages
IDTCV149
DESCRIPTION:
IDTCV149 is a 56 pin clock device for AMD advance K8 processors. The
CPU output buffer is designed to support up to 400MHz processor. This device
also implements Band-gap referenced I
REF
to reduce the impact of V
DD
variation
on differential outputs, which can provide more robust system performance.
Each CPU/SRC clock has its own Spread Spectrum selection, which allows
for isolated changes instead of affecting other clock groups.
KEY SPECIFICATION:
• CPU CLK cycle to cycle jitter < 85ps
• SRC CLK cycle to cycle jitter < 100ps
• Static PLL frequency divide error = 0 ppm
FUNCTIONAL BLOCK DIAGRAM
SRC
SSC
N Programming
SRC
SRC[7:3], 0
PCI0
PCI/
14.318MHz
Osc
SRC PLL
SSC
N Programming
SRC/
SRC[2:1]
CLKREQ0#
CLKREQ1#
TURBO1#
CPU PLL
SSC
N Programming
CPU[1:0]
Host/
HTT66
USB48
Fixed PLL
No SSC
48MHz/
24_48MHz
REF[2:0]
Reset#
OUTPUT TABLE
CPU
2
CLKREQ
2
SRC
8
HTT66
1
PCI
1
TURBO
1
USB48
1
24_48
1
REF
3
RESET#
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
© 2004 Integrated Device Technology, Inc.
MAY 2004
DSC - 6497/2
IDTCV149
PROGRAMMABLE FLEXPC™ CLOCK FOR AMD K8 PROCESSOR ATI RS480
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
XIN
XOUT
V
DD
_48
USB_48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CPU AND SRC SPREAD SPECTRUM
MAGNITUDE CONTROL
V
DD
_REF
V
SS
_REF
REF0
REF1
REF2
V
DD
_PC1
PCI0
V
SS
_PCI
V
DD
_HTT
HTT66
V
SS
_HTT
CPUT0
CPUC0
V
DD
_CPU
V
SS
_CPU
CPUT1
CPUC1
V
SS
_48
(1)
CLK_STOP
SCL
SDA
SMC[2:0]
000
001
010
011
100
101
110
111
%
OFF
- 0.25
- 0.5
- 0.75
±0.125
±0.25
±0.375
±0.5
(1)
SEL24/24_48#
CLKREQ0#
CLKREQ1#
SRCT7
SRCC7
SE SIGNAL STRENGTH SELECTION
Str[1:0]
00
01
10
11
Strength
0.6x
0.8x
1x
1.2x
V
DD
_
SRC
(2)
RESET#
SRCT6
SRCC6
SRCT5
SRCC5
V
DDA
V
SSA
IREF
V
SS
_
SRC
V
DD
_
SRC
SRCT4
SRCC4
SRCT3
SRCC3
(2)
V
SS
_SRC
V
DD
_SRC
SRCT0
SRCC0
PCI (BASED ON SRC = 100MHz)
PCIS[1:0]
00
01
10
11
PCI
33.33
36.36
40
30.77
V
DD
_SRC
V
SS
_SRC
SRCT1
TURBO1
SRCT2
SRCC2
SRCC1
NOTES:
1. Internal 130KΩ pull-down resistor.
2. Tristate at power on to be compatible with ATI pin definition.
SSOP/ TSSOP
TOP VIEW
2
IDTCV149
PROGRAMMABLE FLEXPC™ CLOCK FOR AMD K8 PROCESSOR ATI RS480
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Name
XIN
XOUT
PCI0
HTT66
USB48
Turbo1
CPUC[1:0]
CPUT[1:0]
SRCC[7:0]
SRCT[7:0]
IREF
REF[1:0]
REF2
CLKREQ0#
CLKREQ1#
SDA
SCL
SEL24/24_48#
CLK_STOP
RESET#
Type
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
Pin #
1
2
50
47
4
26
40, 41, 44, 45
12, 13, 16, 17, 18, 19,
22, 23, 24, 25, 27, 28,
29, 30, 33, 34
37
53, 54
52
10
11
8
7
9
6
15
Description
XTAL in
XTAL out
PCI clock
66.66 MHz
48MHz
Turbo frequency select
Differential clock
Differential clock
OUT
OUT
OUT
IN
IN
I/O
IN
IN
IN
OUT,
OD
Differential clock reference current
14.318MHz
14.318MHz
SRC OE control, see bytes 3, 4
SRC OE control, see bytes 3, 4
SMBus data
SMBus clock
Latched select input for 24 or 48MHz output. 1 = 24MHz, 0 = 48MHz.
Active HIGH, drives all clocks to LOW (except CPU clocks)
Reset output signal, Open Drain
3
IDTCV149
PROGRAMMABLE FLEXPC™ CLOCK FOR AMD K8 PROCESSOR ATI RS480
COMMERCIAL TEMPERATURE RANGE
SM PROTOCOL
INDEX BLOCK WRITE PROTOCOL
Bit
1
2-9
10
11-18
19
20-27
28
29-36
37
38-45
46
# of bits
1
8
1
8
1
8
1
8
1
8
1
From
Master
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Description
Start
D2h
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Byte count, N (0 is not valid)
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
:
Nth data byte
Acknowledge
Stop
INDEX BLOCK READ PROTOCOL
Bit
1
2-9
10
11-18
19
20
21-28
29
30-37
38
39-46
47
48-55
# of bits
1
8
1
8
1
1
8
1
8
1
8
1
8
From
Master
Master
Slave
Master
Slave
Master
Master
Slave
Slave
Master
Slave
Master
Slave
Description
Master can stop reading any time by issuing the stop bit without waiting
until Nth byte (byte count bit30-37).
Start
D2h
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Repeated Start
D3h
Ack (Acknowledge)
Byte count, N (block read back of N
bytes), power on is 8
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
:
Ack (Acknowledge)
Nth data byte
Not acknowledge
Stop
Master
Slave
Master
INDEX BYTE WRITE
INDEX BYTE READ
Setting bit[11:18] = starting address, bit[20:27] = 01h.
Setting bit[11:18] = starting address. After reading back the first data byte,
master issues Stop bit.
4
IDTCV149
PROGRAMMABLE FLEXPC™ CLOCK FOR AMD K8 PROCESSOR ATI RS480
COMMERCIAL TEMPERATURE RANGE
BYTE 0
Bit
7
6
5
4
3
2
1
0
Output(s) Affected
SRCT7, SRCC7
SRCT6, SRCC6
SRCT5, SRCC5
SRCT4, SRCC4
SRCT3, SRCC3
SRCT2, SRCC2
SRCT1, SRCC1
SRCT0, SRCT0
Description/Function
Output enable
Output enable
Output enable
Output enable
Output enable
Output enable
Output enable
Output enable
0
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power On
1
1
1
1
1
1
1
1
BYTE 1
Bit
7
6
5
4
3
2
1
0
Output(s) Affected
USB48
REF2
REF1
REF0
24_48MHz
CPUT1, CPUC1
CPUT0, CPUC0
HTT66
Description/Function
Output enable
Output enable
Output enable
Output enable
Output enable
Output enable
Output enable
Output enable
0
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power On
1
1
1
1
1
1
1
1
BYTE 2
Bit
7
6
5
4
3
2
1
0
Output(s) Affected
PCI0
Reserved
PCI0 SEL1
PCI0 SEL0
Reserved
SRCs
CPUT1
CPUT0
Description / Function
Output enable
see PCI select table
0
Tristate
1
Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power On
1
0
0
0
0
0
0
0
SRCT P
WRDWN
drive mode
CPUT1 P
WRDWN
drive mode
CPUT0 P
WRDWN
drive mode
Driven in power down
Driven in power down
Driven in power down
Tristate in power down
Tristate in power down
Tristate in power down
BYTE 3
Bit
7
6
5
4
3
2
1
0
Output(s) Affected
SRC7
SRC6
SRC5
SRC4
SRC3
Reserved
Reserved
SRC0
Description / Function
0
CLKREQ0#
CLKREQ0#
CLKREQ0#
CLKREQ0#
CLKREQ0#
1
CLKREQ1#
CLKREQ1#
CLKREQ1#
CLKREQ1#
CLKREQ1#
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power On
0
0
0
0
0
0
0
0
Controlled by CLKREQB#
or CLKREQA#
Controlled by CLKREQB#
or CLKREQA#
5
CLKREQ0#
CLKREQ1#
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