IDTCV123
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PROGRAMMABLE FLEXPC™
CLOCK FOR P4 PROCESSOR
IDTCV123
FEATURES:
• One high precision PLL for CPU, with SSC and N program-
mable
• One high precision PLL for SRC/PCI/SATA, SSC and N pro-
grammable
• One high precision PLL for 96MHz/48MHz
• Band-gap circuit for differential outputs
• Supports spread spectrum modulation, down spread 0.5%
• Supports SMBus block read/write, index read/write
• Selectable output strength for REF
• Allows for CPU frequency to change to a higher frequency for
maximum system computing power
• Available in SSOP package
DESCRIPTION:
IDTCV123 is a 56 pin clock device. The CPU output buffer is designed to
support up to 400MHz processor. This chip has three PLLs inside for CPU/
SRC/PCI, SATA, and 48MHz/DOT96 IO clocks. One dedicated PLL for Serial
ATA clock provides high accuracy frequency. This device also implements
Band-gap referenced I
REF
to reduce the impact of V
DD
variation on differential
outputs, which can provide more robust system performance.
Static PLL frequency divide error can be as low as 36 ppm, worse case 114
ppm, providing high accuracy output clock. Each CPU/SRC/PCI, SATA clock
has its own Spread Spectrum selection, which allows for isolated changes
instead of affecting other clock groups.
OUTPUTS:
• 2*0.7V current –mode differential CPU CLK pair
• 8*0.7V current –mode differential SRC CLK pair, one dedicated
for SATA
• One CPU_ITP/SRC selectable CLK pair
• 8*PCI, 3 free running, 33.3MHz
• 1*96MHz, 1*48MHz
• 2*REF
KEY SPECIFICATION:
•
•
•
•
•
CPU/SRC CLK cycle to cycle jitter < 85ps
SATA CLK cycle to cycle jitter < 85ps
PCI CLK cycle to cycle jitter < 250ps
Static PLL frequency divide error < 114 ppm
Static PLL frequency divide error for 48MHz < 5 ppm
FUNCTIONAL BLOCK DIAGRAM
PLL1
SSC
N Programmable
CPU CLK
Output Buffers
Stop Logic
CPU[1:0]
X1
XTAL
Osc Amp
CPU_ITP/SRC6
I
REF
REF[0:1]
ITP_EN
X2
SDATA
SCLK
SM Bus
Controller
PLL2
SSC
N Programmable
SRC CLK
Output Buffer
Stop Logic
SRC[6:0]
SATA_SRC
PCI[5:0], PCIF[2:0]
I
REF
V
TT_PWRGD
#/PD
Control
Logic
FSA.B.C
PLL3
48MHz/96MHz
Output BUffer
DOT96
48MHz
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
© 2004 Integrated Device Technology, Inc.
MAY 2004
DSC-6538/6
IDTCV123
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
PCI0
PCI1
V
DD
_PCI
GND_PCI
PCI2
PCI3
PCI4
PCI5
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
DDA
Description
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage GND - 0.5
Storage Temperature
Ambient Operating Temperature
Case Temperature
Input ESD Protection
Human Body Model
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Min
Max
4.6
4.6
+150
+70
+115
Unit
V
V
°C
°C
°C
V
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
V
DD
_REF
REF0/FSC
REF1/FSA
GND_REF
X
1
X
2
SDAT
SCL
GND_CPU
CPU0
CPU0#
V
DDIN
T
STG
T
AMBIENT
T
CASE
ESD Prot
–65
0
2000
GND_PCI
V
DD
_PCI
*TEST_SEL/PCIF0
ITP_EN/PCIF1
V
DD
48
USB48/FSB
V
DD
_CPU
CPU1
CPU1#
GND
48
DOT96
DOT96#
IREF
GND_A
V
DD
_A
CPU_ITP/SRC6
CPU_ITP#/SRC6#
ITP_EN
1
0
pin 38
CPUC2_ITP
SRCC6
pin 39
CPUT_ITP
SRCT6
V
TT
_P
WRGD#
/
PD
SRC0
SRC0#
SRC1
SRC1#
V
DD
_SRC
SRC5
SRC5#
TEST CLARIFICATION TABLE
HW
SW
TEST_SEL/ TEST SELECT
PCICLK_F0
BIT B6b6
OUTPUT
0
0
Normal
1
X
Hi-Z
Comments
Normal Operation
Power-up with TEST_SEL =1 to
enter test mode. Cycle power with
TEST_SEL = 0 to disable test mode
If TEST_SEL HW pin is 0 during
power-up, test mode can be invoked
through B6b6. Cycle power with
TEST_SEL = 0 to disable test mode.
V
DD
_SRC
GND_SRC
SRC2
SRC2#
SATA_SRC
SATA_SRC#
GND_SRC
SRC4
SRC4#
SRC3
SRC3#
0
1
Hi-Z
V
DD
_SRC
* = Internal pull down
SSOP
TOP VIEW
FREQUENCY SELECTION TABLE
FSC, B, A
101
001
011
010
000
100
110
111
CPU Mode, MHz
100
133
166
200
266
333
400
Reserve
SRC4
100
100
100
100
100
100
100
100
SRC[3:1], SRC[7:5]
100
100
100
100
100
100
100
100
2
PCI
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
USB
48
48
48
48
48
48
48
48
DOT96
96
96
96
96
96
96
96
96
REF
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
IDTCV123
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Name
PCI0
PCI1
V
DD
_PCI
V
SS
_PCI
PCI2
PCI3
PCI4
PCI5
V
SS
_PCI
V
DD
_PCI
TEST_SEL/PCIF0
ITP_EN/PCIF1
V
DD
48
USB48 /FS_B
V
SS
48
DOT96T
DOT96C
V
TT
_P
WRGD
#/PD
Type
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
GND
PWR
I/O
OUT
PWR
I/O
GND
OUT
OUT
I/O
Description
PCI clock
PCI clock
3.3V
GND
PCI clock
PCI clock
PCI clock
PCI clock
GND
3.3V
Test Select (sampled at V
TT
_P
WRGD
# assertion), see TEST_SEL table. PCI clock afterward, free
running.
Pin38, 39, CPU_ITP/SRC6 select (sampled on V
TT
_P
WRGD
# assertion), HIGH = CPU_2PCI
clock. PCI clock afterward, running.
3.3V
48MHz clock/ FS_B input
GND
96MHz 0.7V current mode differential clock output
96MHz 0.7V current mode differential clock output
3.3V LVTTL input is a level-sensitive strobe used to latch the FS_A, FS_B, FS_C, TEST_SEL and
ITP_EN inputs, V
TT
_P
WRGD
# is low assertion/ After V
TT
_P
WRGD
# assertion, becomes a real-time
input for asserting power down (active HIGH).
Differential Serial reference clock
Differential Serial reference clock
Differential Serial reference clock
Differential Serial reference clock
3.3V
GND
Differential Serial reference clock
Differential Serial reference clock
SATA clock
SATA clock
3.3V
Differential Serial reference clock
Differential Serial reference clock
Differential Serial reference clock
Differential Serial reference clock
GND
Differential Serial reference clock
Differential Serial reference clock
3.3V
Selectable CPU or SRC differential clock output. ITP_EN=0 @ V
TT
_P
WRGD
# assertion = SRCC6.
Selectable CPU or SRC differential clock output. ITP_EN=0 @ V
TT
_P
WRGD
# assertion = SRCT6.
3.3V
GND
Reference current for differential output buffer
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
SRCT0
SRCC0
SRCT1
SRCC1
V
DD
_SRC
V
SS
_SRC
SRCT2
SRCC2
SRCT_SATA
SRCC_SATA
V
DD
_SRC
SRCC3
SRCT3
SRCC4
SRCT4
V
SS
_SRC
SRCC5
SRCT5
V
DD
_SRC
CPUC2_ITP/ SRCC6
CPUT2_ITP/ SRCT6
V
DD
_A
V
SS
_A
IREF
OUT
OUT
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
PWR
OUT
OUT
OUT
OUT
GND
OUT
OUT
PWR
OUT
OUT
PWR
GND
OUT
3
IDTCV123
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONT.)
Pin Number
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Name
CPUC1
CPUT1
V
DD
_CPU
CPUC0
CPUT0
V
SS
_CPU
SCL
SDA
XTAL_OUT
XTAL_IN
V
SS
_REF
REF1/ FSA
REF0/ FSC
V
DD
_REF
Type
OUT
OUT
PWR
OUT
OUT
GND
IN
I/O
OUT
IN
GND
I/O
I/O
PWR
Description
Host 0.7V current mode differential clock output
Host 0.7V current mode differential clock output
3.3V
Host 0.7V current mode differential clock output
Host 0.7V current mode differential clock output
GND
SM bus clock
SM bus data
Xtal output
Xtal input
GND
14.318 MHz reference clock output. CPU frequency selection at V
TT
_P
WRGD
# assertion.
14.318 MHz reference clock output. CPU frequency selection at V
TT
_P
WRGD
# assertion.
3.3V
INDEX BLOCK WRITE PROTOCOL
Bit
1
2-9
10
11-18
19
20-27
28
29-36
37
38-45
46
# of bits
1
8
1
8
1
8
1
8
1
8
1
From
Master
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Description
Start
D2h
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Byte count, N, (0 is not valid
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
:
Nth data byte
Acknowledge
Stop
INDEX BLOCK READ PROTOCOL
Master can stop reading any time by issuing the stop bit without waiting
until Nth byte (byte count bit30-37).
Bit
1
2-9
10
11-18
19
20
21-28
29
30-37
38
39-46
47
48-55
# of bits
1
8
1
8
1
1
8
1
8
1
8
1
8
From
Master
Master
Slave
Master
Slave
Master
Master
Slave
Slave
Master
Slave
Master
Slave
Description
Start
D2H
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Repeated Start
D3H
Ack (Acknowledge)
Byte count, N (block read back of N
bytes), power on is 8
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
:
Ack (Acknowledge)
Nth data byte
Not acknowledge
Stop
Master
Slave
Master
INDEX BYTE WRITE
Setting bit[11:18] = starting address, bit[20:27] = 01h.
INDEX BYTE READ
Setting bit[11:18] = starting address. After reading back the first data byte,
master issues Stop bit.
4
IDTCV123
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
CONTROL REGISTERS
N PROGRAMMING PROCEDURE
•
•
Use Index byte write.
For N programming, the user only needs to access Byte17, Byte 25, and Byte8.
1.
2.
3.
Write Byte17 for CPU PLL N, CPU f = N* Resolution, see resolution table below Byte17.
Write Byte25 for SRC PLL N, SRC f = N*0.666667, PCI = SRC f /3, SATA f = SRC f.
Enable N Programming bit, Byte8 bit1. Once this bit is enabled, any N value will be changed on the fly.
•
•
•
Center spread only works when the N Programming bit is enabled. Down spread is OK even N Programming bit is disabled
It is OK to change N value to any value on the bench test board. In the system, IDT recommends the stepping change. It is unknown how much
the system can sustain for each stepping change; the estimate is about 5. If the N changes too much in one step, the system will likely hang.
Note that SATA is with SRC PLL. This SATA Hard Drive might not operate during SRC N programming.
Most of the Bytes, from Byte8-Byte31, are used to adjust output waveforms and SSC modulation profiles. The power on setting will be changed according
to each power on frequency selection. To avoid mistakes, don’t write on those byte (be careful about Block Write). It is suggested to use the Index Byte
write to access bytes.
SSC MAGNITUDE CONTROL, SMC
SMC[2:0]
000
001
010
011
100
101
110
111
-0.25
-0.5
-0.75
-1
±0.125
±0.25
±0.375
±0.5
FREQUENCY SELECTION TABLE
FS_C, B, A
101
001
011
010
000
100
110
111
CPU
100
133
166
200
266
333
400
RESERVE
RESOLUTION
CPU (MHz)
100
133
166
200
266
333
400
Resolution
0.666667
0.666667
1.333333
1.333333
1.333333
2.666667
2.666667
N=
150
200
125
150
200
125
150
5
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