TB6556F/FG
TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic
TB6556F/FG
3-Phase Full-Wave Sine-Wave PWM Brushless Motor Controller
Features
•
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•
•
•
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Sine-wave PWM control
Built-in triangular-wave generator
(carrier cycle = f
osc
/252 (Hz))
Built-in lead angle control function (0° to 58° in 32 steps)
External setting/automatic internal setting
Built-in dead time function (setting 2.6 µs or 3.8 µs)
Supports bootstrap circuit
Overcurrent protection signal input pin
Built-in regulator (V
refout
= 5 V (typ.), 30 mA (max))
Operating supply voltage range: V
CC
= 6 V to 10 V
Weight: 0.33 g (typ.)
TB6556FG:
TB6556FG is a Pb-free product.
The following conditions apply to solderability:
*Solderability
1. Use of Sn-63Pb solder bath
*solder bath temperature = 230˚C
*dipping time = 5 seconds
*number of times = once
*use of R-type flux
2. Use of Sn-3.0Ag-0.5Cu solder bath
*solder bath temperature = 245˚C
*dipping time = 5 seconds
*the number of times = once
*use of R-type flux
1
2005-01-19
TB6556F/FG
Block Diagram
G
out
PH
LL
29
26
+
Filter
Lower limit
6-bit triangular
wave generator
5-bit AD
Phase U
Counter
Data
select
Phase V
Comparator
Comparator
Phase W
Comparator
9 U
6 X
8 V
5 Y
7 W
120/180
Charger
FG
Rotating
direction
HU
HV
HW
Comparator
PWM
4 Z
Output
waveform
generator
Upper limit
27
28
30
LPF
LA
UL
25
G
in
24
Peak hold
X
in
14
System clock
generator
X
out
15
10 Td
HU 21
HV 20
Position detector
HW 19
V
e
2
V
CC
1
Regulator
Internal
Phase
reference matching
voltage
Setting
dead
time
GND 13
V
refout
23
Power-on
reset
Switching
120°/180°
and
gate block
protection
on/off
120°-
turn-on
matrix
12 OS
RES 11
I
dc
3
CW/CCW 18
SS 22
ST/SP
CW/CCW
Protection
ERR
&
GB
reset
FG 17
EV 16
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2005-01-19
TB6556F/FG
Pin Description
Pin No.
21
20
19
18
Symbol
HU
HV
HW
CW/CCW
Description
Positional signal input pin U
Positional signal input pin V
Positional signal input pin W
Rotation direction signal input
pin
Reset-signal-input pin
Voltage command signal
Gain setting
L: Forward
H: Reverse
L: Reset (output is non-active)
operation/halt operation, also used for gate protection,
built-in pull-up resistor
With built-in pull-down resistor
I
dc
signal level at a gain that optimizes the LA
Connect the peak-hold capacitor and discharge resistor to GND, parallel
to each other
Connect the low-pass filter capacitor (built-in 100 kΩ resistor)
Sets 0° to 58° in 32 steps
Set lower limit for LA (LL
=
0 V to 5.0 V)
Set upper limit for LA (UL
=
0 V to 5.0 V)
L: Active LOW
H: Active HIGH
Inputs DC link current.
Reference voltage: 0.5 V
With built-in filter (
∼
1
µs),
built-in digital filter (
∼
1
µs)
−
−
With built-in feedback resistor
When positional signal is HHH or LLL, gate block protection operates.
With built-in pull-up resistor, built-in digital filter (
∼
500 ns)
−
Remarks
11
2
24
25
26
27
28
29
30
12
RES
V
e
G
in
G
out
PH
LPF
LA
LL
UL
OS
Peak hold
RC low-pass filter
Lead angle setting signal
input pin
Lower limit for LA
Upper limit for LA
Inputs output logic select
signal
Inputs overcurrent protection
signal
Inputs clock signal
Outputs clock signal
Outputs reference voltage
signal
FG signal output pin
Reverse rotation detection
signal
Outputs turn-on signal
Outputs turn-on signal
Outputs turn-on signal
3
14
15
23
17
16
9
8
7
6
5
4
1
10
22
13
I
dc
X
in
X
out
V
refout
FG
REV
U
V
W
X
Y
Z
V
CC
Td
SS
GND
5 V (typ.), 30 mA (max)
Outputs 3 PPR of positional signal
Detects reverse rotation.
Select active HIGH or active LOW using the output logic select pin.
Outputs turn-on signal
Outputs turn-on signal
Outputs turn-on signal
Power supply voltage pin
Inputs setting dead time
120°/180° select signal
Ground pin
V
CC
=
6 to 10 V
L: 3.8
µs,
H or OPEN: 1.9
µs
L: 120° turn-on mode, H or OPEN: 180° turn-on mode
⎯
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2005-01-19
TB6556F/FG
Input/Output Equivalent Circuits
Pin Description
Symbol
Input/Output Signal
Input/Output Internal Circuit
Digital
Positional signal input pin U
Positional signal input pin V
Positional signal input pin W
HU
HV
HW
With Schmitt trigger
Hysteresis 300 mV (typ.)
Digital filter: 500 ns (typ.)
L: 0.8 V (max)
H: V
refout
−
1 V (min)
V
refout
V
refout
200 kΩ
2.0 kΩ
V
refout
V
refout
2.0 kΩ
V
refout
V
refout
2.0 kΩ
V
refout
V
refout
200 kΩ
2.0 kΩ
V
CC
100
Ω
150 kΩ
100 kΩ
100 kΩ
Forward/reverse switching
input pin
CW/CCW
L: Forward (CW)
H: Reverse (CCW)
Digital
L: 0.8 V (max)
H: V
refout
−
1 V (min)
Reset input
L: Stops operation (reset)
H: Operates
RES
Digital
L: 0.8 V (max)
H: V
refout
−
1 V (min)
Digital
120°/180° select signal
SS
L: 120° turn-on mode
H: 180° turn-on mode
(OPEN)
With Schmitt trigger
Hysteresis: 300 mV (typ.)
L: 0.8 V (max)
H: V
refout
−
1 V (min)
Voltage command signal
1.0 V
<
Ve
≤
2.1 V
Refresh operation
(X, Y, Z pins: ON duty of
8%)
V
e
Analog
Input voltage range 0 to 5.4 V
Input voltage of 5.4 V or higher is
clipped to 5.4 V.
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2005-01-19
TB6556F/FG
Pin Description
Symbol
Input/Output Signal
When LA is fixed externally, connect
LL to GND and UL to V
refout
, and then
input the setting voltage to the LA pin.
Lead angle setting signal
input pin
0 V: 0°
5 V: 58°
(5-bit AD)
LA
Input voltage of V
refout
or higher is
clipped to V
refout
.
When LA is fixed automatically, open
the LA pin. In this state, the LA pin is
used only for confirmation of LA width.
Input voltage range: 0 V to 5.0 V
(V
refout
)
Input/Output Internal Circuit
V
CC
100
Ω
200 kΩ
Automatic LA
circuit
V
CC
Non-inverted amplifier
25 dB (max)
G
out
output voltage
LOW: GND
HIGH: V
CC
−
1.7 V
V
CC
Gain setting signal input
(LA setting)
G
in
G
out
G
in
100
Ω
G
out
I
dc
To peak
hold circuit
V
CC
Connect the peak-hold capacitor and
discharge resistor to GND, parallel to
each other.
100 kΩ/0.1µF recommended
Peak hold
(LA setting)
PH
100
Ω
100
Ω
V
CC
Connect the low-pass filter capacitor
(built-in 100 kΩ resistor)
0.1µF recommended
Low-pass filter
(LA setting)
LPF
100 kΩ
100
Ω
V
CC
Clip lower limit for LA
LL
=
0 V to 5.0 V
When LL
>
UL, LA is fixed at LL value.
Lower limit for LA
LL
100
Ω
5
2005-01-19
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