5812-F
UCQ5812EPF
SERIAL
DATA OUT
LOGIC
SUPPLY
LOAD
SUPPLY
OUT
20
SERIAL
DATA IN
OUT
19
OUT
1
BiMOS II 20-BIT SERIAL-INPUT, LATCHED
SOURCE DRIVERS FOR -40
°
C TO +85
°
C OPERATION
The UCQ5812AF/EPF combine a 20-bit CMOS shift register, data
latches, and control circuitry with high-voltage bipolar source drivers and
active DMOS pull-downs for reduced supply current requirements. Although
designed primarily for vacuum-fluorescent displays, the high-voltage, high-
current outputs also allow them to be used in other peripheral power driver
applications.
25
24
OUT
2
OUT
18
5
6
REGISTER
LATCHES
LATCHES
7
8
9
10
OUT
12
11
23
22
21
20
19
OUT
8
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 5 V supply, they will operate to at
least 3.3 MHz. At 12 V, higher speeds are possible. Especially useful for
inter-digit blanking, the BLANKING input disables the output source drives
and turns on the DMOS sink drivers. Use with TTL may require the use of
appropriate pull-up resistors to ensure an input logic high.
A CMOS serial data output enables cascade connections in applications
requiring additional drive lines. Similar devices are available as the
UCQ5810AF/LWF (10 bits), UCQ5811A (12 bits), and UCQ5818AF/EPF
(32 bits).
ABSOLUTE MAXIMUM RATINGS
at T
A
= 25°C
Logic Supply Voltage, V
DD
.....................
15 V
Driver Supply Voltage, V
BB
....................
60 V
Continuous Output Current Range,
I
OUT
.................................
-40 to +15 mA
Input Voltage Range,
V
IN
........................
-0.3 V to V
DD
+ 0.3 V
Package Power Dissipation, P
D
(UCQ5812AF) ...........................
3.12 W*
(UCQ5812EPF) ........................1.84
W†
Operating Temperature Range,
T
A
..................................
-40
°
C to +85
°
C
Storage Temperature Range,
T
S
................................
-55
°
C to +150
°
C
* Derate at rate of 22 mW/°C above T
A
= +25°C
† Derate at rate of 15 mW/°C above T
A
= +25°C
D
NC
ent
E
E
U
R
em
IN
FE
lac
T
E
p
N
R
re
O
R
d
C
O
de
IS
F
en
D
—
m
OUT
11
GROUND
BLANKING
STROBE
CLOCK
OUT
10
OUT
9
Dwg. PP-059-1
The output source drivers are high-voltage PNP-NPN Darlingtons with a
minimum breakdown of 60 V and are capable of sourcing up to 40 mA. The
DMOS active pull-downs are capable of sinking up to 15 mA.
T
C
U
Y
2
D
L
81
O
N
6
R
O
A
P
E
—
Data Sheet
26182.27B
REGISTER
CLK
12
14
ST
V
DD
28
V
BB
17
27
13
15
16
18
26
4
3
2
1
The UCQ5812AF is supplied in a 28-pin dual in-line plastic package with
0.600" (15.24 mm) row spacing. For surface mounting, the UCQ5812EPF is
furnished in 28-lead plastic chip carrier (quad pack) with 0.050"(1.22 mm)
centers. Copper lead-frames, reduced supply current requirements and lower
output saturation voltages, allow continuous operation, with all outputs
sourcing 25 mA, of the UCQ5812AF over the operating temperature range,
and the UCQ5812EPF up to +75°C.
FEATURES
s
s
s
s
s
Caution: Allegro CMOS devices have input static
protection but are susceptible to damage when
exposed to extremely high static electrical
charges.
Note that the UCQ5812AF (dual in-line package)
and UCQ5812EPF (PLCC package) are
electrically identical and share a common pin
number assignment.
m
o
c
e
R
High-Speed Source Drivers
60 V Source Outputs
To 3.3 MHz Data Input Rate
Low-Output Saturation Voltages
Low-Power CMOS Logic and Latches
s
Active DMOS Pull-Downs
s
Reduced Supply Current
Requirements
s
Improved Replacement
for TL5812
Always order by complete part number, e.g.,
UCQ5812AF .
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FOR -40
°
C TO +85
°
C OPERATION
CLOCK
DATA IN
C
STROBE
BLANKING
G
OUT
N
Dwg. No. 12,649A
A
B
D
E
F
Serial Data present at the input is transferred
to the shift register on the logic “0” to logic “1”
transition of the CLOCK input pulse. On succeed-
ing CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUT-
PUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input
waveform.
Information present at any register is trans-
ferred to the respective latch when the STROBE
is high (serial-to-parallel conversion). The latches
will continue to accept
new data as long as the STROBE is held high.
Applications where the latches are bypassed
(STROBE tied high) will require that the
BLANKING input be high during serial data
entry.
When the BLANKING input is high, the
output source drivers are disabled (OFF); the
DMOS sink drivers are ON, the information
stored in the latches is not affected by the
BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of
their respective latches.
TIMING REQUIREMENTS
(T
A
= +25°C,V
DD
= 5 V, Logic Levels are V
DD
and Ground)
A.
Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75 ns
B.
Minimum Data Active Time After Clock Pulse
(Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75 ns
C.
Minimum Data Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
150 ns
D.
Minimum Clock Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
150 ns
E.
Minimum Time Between Clock Activation and Strobe . . . . . . . . . . .
300 ns
F.
Minimum Strobe Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100 ns
G.
Typical Time Between Strobe Activation and
Output Transistion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
500 ns
Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable
with increased supply voltage; operation at high temperatures will reduce the
specified maximum clock frequency.
TRUTH TABLE
Serial
Data Clock
Input Input
H
L
X
Shift Register Contents
I
1
H
L
I
2
I
3
…
I
N-1
I
N
R
N-2
R
N-1
R
N-2
R
N-1
R
N-1
R
N
X
X
Serial
Data Strobe
Output Input
R
N-1
R
N-1
R
N
X
P
N
X = Irrelevant
Latch Contents
I
1
I
2
I
3
…
I
N-1
I
N
Blanking
I
1
Output Contents
I
2
I
3
…
I
N-1
I
N
R
1
R
2
…
R
1
R
2
…
R
1
R
2
R
3
…
X
X
X
…
L
H
R
1
R
2
R
3
…
P
1
P
2
P
3
…
X
X
X
…
R
N-1
R
N
P
N-1
P
N
X
X
L
H
P
1
P
2
P
3
…
L
L
L
…
P
N1
P
N
L
L
P
1
P
2
P
3
…
L = Low Logic Level
P
N-1
P
N
H = High Logic Level
P = Present State R = Previous State
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