®
RT8880B
Dual-Output PWM Controller with 3 Integrated Drivers for
AMD SVI2 Mobile CPU Power Supply
General Description
The RT8880B is a 3 + 2 phases PWM controller, and is
compliant with AMD SVI2 Voltage Regulator Specification
to support both CPU core (VDD) and Northbridge portion
of the CPU (VDDNB). The RT8880B features CCRCOT
(Constant Current Ripple Constant On-Time) with G-NAVP
(Green-Native AVP), which is Richtek's proprietary
topology. The G-NAVP makes it an easy setting controller
to meet all AMD AVP (Adaptive Voltage Positioning) VDD/
VDDNB requirements. The droop is easily programmed
by setting the DC gain of the error amplifier. With proper
compensation, the load transient response can achieve
optimized AVP performance. The controller also uses the
interface to issue VOTF Complete and to send digitally
encoded voltage and current values for the VDD and
VDDNB domains. It can operate in single phase and diode
emulation mode and reach up to 90% efficiency in different
modes according to different loading conditions. The
RT8880B provides special purpose offset capabilities by
pin setting. The RT8880B also provides power good
indication, over-current indication (OCP_L) and dual OCP
mechanism for AMD SVI2 CPU core and NB. It also
features complete fault protection functions including over-
voltage, under-voltage and negative-voltage protections.
Features
3/2/1-Phase (VDD) + 2/1-Phase (VDDNB) PWM
Controller
3 Embedded MOSFET Drivers
G-NAVP
TM
Topology
Support Dynamic Load-Line and Zero Load-Line
Diode Emulation Mode at Light Load Condition
SVI2 Interface to Comply with AMD Power
Management Protocol
Build-in ADC for V
OUT
and I
OUT
Reporting
Immediate OV, UV and NV Protections and UVLO
Programmable Dual OCP Mechanism
0.5% DAC Accuracy
Fast Transient Response
Power Good Indicator
Over-Current Indicator
52-Lead WQFN Package
RoHS Compliant and Halogen Free
Applications
AMD SVI2 Mobile CPU
Laptop Computer
Simplified Application Circuit
RT8880B
PHASE1
OCP_L
SVC
To CPU
SVD
SVT
PHASE2
PWM3
PHASEA1
PWMA2
MOSFET
MOSFET
RT9610
MOSFET
RT9610
MOSFET
MOSFET
V
VDD
V
VDDNB
Copyright
©
2014 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS8880B-02 January 2014
www.richtek.com
1
RT8880B
Ordering Information
RT8880B
Package Type
QW : WQFN-52L 6x6 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
Note :
Richtek products are :
RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
UGATE2
BOOT2
PWM3
TONSET
ISEN2P
ISEN2N
ISEN1N
ISEN1P
ISEN3P
ISEN3N
VSEN
FB
COMP
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20 21 22 23 24 25 26
53
Pin Configurations
(TOP VIEW)
PHASE2
LGATE2
PVCC
LGATE1
PHASE1
UGATE1
BOOT1
LGATEA1
PHASEA1
UGATEA1
BOOTA1
PWMA2
TONSETA
52 51 50 49 48 47 46 45 44 43 42 41 40
39
38
37
36
35
34
GND
33
32
31
30
29
28
27
Marking Information
RT8880BGQW : Product Number
Copyright
©
2014 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
2
RGND
IMON
V064
IMONA
VDDIO
PWROK
SVC
SVD
SVT
OFS
OFSA
SET1
SET2
RT8880B
GQW
YMDNN
YMDNN : Date Code
PGOOD
PGOODA
EN
ISENA1P
ISENA1N
ISENA2N
ISENA2P
VSENA
FBA
COMPA
IBIAS
VCC
OCP_L
WQFN-52L 6x6
DS8880B-02 January 2014
RT8880B
Functional Pin Description
Pin No.
3
4
5, 8, 9
6, 7, 10
11
12
13
14
15
16
17
Pin Name
PWM3
TONSET
ISEN1P to ISEN3P
ISEN1N to ISEN3N
VSEN
FB
COMP
RGND
IMON
V064
IMONA
Pin Function
PWM Outputs for Channel 3 VDD Controller.
VDD Controller On-Time Setting. Connect this pin to the converter input
voltage, VIN, through a resistor, RTON, to set the on-time of UGATE and
also the output voltage ripple of VDD controller.
Positive Current Sense Input of Channel 1, 2 and 3 for VDD Controller.
Negative Current Sense Input of Channel 1, 2 and 3 for VDD Controller.
VDD Controller Voltage Sense Input. This pin is connected to the terminal
of VDD controller output voltage.
Output Voltage Feedback Input of VDD Controller. This pin is the negative
input of the error amplifier for the VDD controller.
Compensation Node of the VDD Controller.
Return Ground of VDD and VDDNB Controller. This pin is the common
negative input of output voltage differential remote sense for VDD and
VDDNB controllers.
Current Monitor Output for the VDD Controller. This pin outputs a voltage
proportional to the output current.
Fixed 0.64V Output Reference Voltage Output. This voltage is only used to
offset the output voltage of IMON pin and IMONA pin. Connect a 0.47μF
capacitor from this pin to GND.
Current Monitor Output for the VDDNB Controller. This pin outputs a
voltage proportional to the output current.
Processor Memory Interface Power Rail and Serves as the Reference for
PWROK, SVD, SVC and SVT. This pin is used by the VR to reference the
SVI pins.
System Power Good Input. If PWROK is low, the SVI interface is disabled
and VR returns to BOOT-VID state with initial load line slope and initial
offset. If PWROK is high, the SVI interface is running and the DAC
decodes the received serial VID codes to determine the output voltage.
Serial VID Clock Input from Processor.
Serial VID Data input from Processor. This pin is a serial data line.
Serial VID Telemetry Input from VR. This pin is a push-pull output.
Over Clocking Offset Setting for the VDD Controller.
Over Clocking Offset Setting for the VDDNB Controller.
1st Platform Setting. Platform can use this pin to set OCP_TDC threshold,
DVID compensation bit1 and internal ramp slew rate.
2st Platform Setting. Platform can use this pin to set quick response
threshold, OCP_TDC trigger delay time, DVID compensation bit0, VDDNB
rail zero load-line enable setting and over clocking offset enable setting.
Over-Current Indicator for Dual OCP Mechanism. This pin is an open-drain
output.
Controller Power Supply Input. Connect this pin to 5V with an 1μF or
greater ceramic capacitor for decoupling.
18
VDDIO
19
PWROK
20
21
22
23
24
25
SVC
SVD
SVT
OFS
OFSA
SET1
26
SET2
27
28
OCP_L
VCC
Copyright
©
2014 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS8880B-02 January 2014
www.richtek.com
3
RT8880B
Pin No.
29
30
31
32
33, 36
34, 35
37
38
39
40
41
46, 2, 42
Pin Name
IBIAS
COMPA
FBA
VSENA
ISENA2P,
ISENA1P
ISENA2N,
ISENA1N
EN
PGOODA
PGOOD
TONSETA
PWMA2
BOOT1,
BOOT2,
BOOTA1
UGATE1,
UGATE2,
UGATEA1
PHASE1,
PHASE2,
PHASEA1
LGATE1,
LGATE2,
LGATEA1
PVCC
GND
Pin Function
Internal Bias Current Setting. Connect only a 100kΩ resistor from this pin to
GND to generate bias current for internal circuit. Place this resistor as close to
the IBIAS pin as possible.
Compensation Node of the VDDNB Controller.
Output Voltage Feedback Input of VDDNB Controller. This pin is the negative
input of the error amplifier for the VDDNB controller.
VDDNB Controller Voltage Sense Input. This pin is connected to the terminal
of VDDNB controller output voltage.
Positive Current Sense Input of Channel 1 and 2 for VDDNB Controller.
Negative Current Sense Input of Channel 1 and 2 for VDDNB Controller.
Controller Enable Control Input. A logic high signal enables the controller.
Power Good Indicator for the VDDNB Controller. This pin is an open-drain
output.
Power Good Indicator for the VDD Controller. This pin is an open-drain output.
VDDNB Controller On-Time Setting. Connect this pin to the converter input
voltage, VIN, through a resistor, RTONNB, to set the on-time of
UGATE_VDDNB and also the output voltage ripple of VDDNB controller.
PWM Output for Channel 2 of VDDNB Controller.
Bootstrap Supply for High-Side MOSFET. This pin powers high-side MOSFET
driver.
High-Side Gate Driver Outputs. Connect this pin to Gate of high-side
MOSFET.
Switch Nodes of High-Side Driver. Connect this pin to high-side MOSFET
Source together with the low-side MOSFET Drain and the inductor.
47, 1, 43
48, 52, 44
49, 51, 45
50
53 (Exposed Pad)
Low-Side Gate Driver Outputs. This pin drives the Gate of low-side MOSFET.
Driver Power. Connect this pin to GND by ceramic capacitor larger than 1μF.
Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
Copyright
©
2014 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
4
DS8880B-02 January 2014
RT8880B
Function Block Diagram
PWROK
VDDIO
SVD
SVC
SVT
PGOODA
PGOOD
VSEN
VSENA
OCP_L
OFSA
SET1
SET2
VCC
UVLO
OFS
EN
MUX
ADC
IBIAS
From Control Logic
RGND
DAC
VSETA
ERROR
AMP
+
-
IMONI
IMONAI
GND
SVI2 Interface
Configuration Registers
Control Logic
OFS/OFSA
Load Line
/Load Line A
RSET/RSETA
OCP Threshold
Loop Control
Protection Logic
TONSETA
PWMA2
Soft-Start & Slew
Rate Control
FBA
COMPA
ISENA1P
ISENA1N
Offset
Cancellation
+
+
-
PWM
CMPA
QRA
TONA
TON
GENA PWMA1
1-PH
Driver
BOOTA1
UGATEA1
PHASEA1
LGATEA1
Current mirror
+
x2
-
IBA1
V064
Current mirror
+
0.4
-
RSETA
Average
IMONAI
Current
Balance
IBA1
IBA2
Driver
POR
PVCC
ISENA2P
ISENA2N
IMONA
From Control Logic
RGND
DAC
Soft-Start & Slew Rate
Control
+
x2
-
IBA2
OCP_TDCA,
OCP_SPIKEA
+
-
OCA
To Protection Logic
OV/UV/NV
PWM1
TONSET
BOOTx
2-PH
Driver
UGATEx
PHASEx
LGATEx
PWM3
TON
VSENA
ERROR
AMP
+
-
VSET
FB
COMP
Offset
Cancellation
+
+
Current mirror
ISEN1P
ISEN1N
+
x1
-
-
PWM
CMP
QR
TON
GEN
PWM2
IB1
+
0.4
-
Current mirror
ISEN2P
ISEN2N
+
x1
-
RSET
Current Balance
Average
IMONI
IB1
IB2
IB3
IB2
Current mirror
ISEN3P
ISEN3N
+
x1
-
IB3
OCP_TDC,
OCP_SPIKE
+
-
OC
To Protection Logic
OV/UV/NV
VSEN
IMON V064
Copyright
©
2014 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS8880B-02 January 2014
www.richtek.com
5
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