Si53152
P C I - E
X P R E S S
G
EN
1, G
E N
2 , G
EN
3,
A N D
G
E N
4
F
ANOUT
B
UFFER
Features
PCI-Express Gen 1, Gen 2, Gen 3,
and Gen 4 common clock
compliant
Supports Serial ATA (SATA) at
100 MHz
100–210 MHz operation
Low power, push pull, differential
output buffers
Internal termination for maximum
integration
Dedicated output enable pin for
each clock
Two PCI-Express buffered clock
outputs
Supports LVDS outputs
I
2
C support with readback
capabilities
Extended temperature:
–40 to 85
o
C
3.3 V Power supply
24-pin QFN package
Ordering Information:
See page 17
Applications
Network attached storage
Multi-function Printer
Wireless access point
Routers
Pin Assignments
SDATA
20
DIFFIN
DIFFIN
Description
VDD
1
2
3
4
5
6
VDD
VSS
24
23
22
21
SCLK
19
18 OE_DIFF1*
17 VDD
16 DIFF1
15 DIFF1
14 DIFF0
13 DIFF0
12
The Si53152 is a spread spectrum tolerant PCIe clock buffer that can source
two PCIe clocks simultaneously. The device has two hardware output enable
inputs for enabling the respective differential outputs on the fly. The device
also features output enable control through I
2
C communication. I
2
C
programmability is also available to dynamically control skew, edge rate and
amplitude on the true, compliment, or both differential signals on the clock
outputs. This control feature enables optimal signal integrity as well as
optimal EMI signature on the clock outputs. Measuring PCIe clock jitter is
quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for
free at
www.silabs.com/pcie-learningcenter.
NC
VDD
VSS
OE_DIFF0*
VDD
25
GND
7
8
9
10
11
NC
NC
NC
NC
*Note:
Internal 100 kohm pull-up.
Patents pending
Functional Block Diagram
DIFF0
DIFFIN
DIFFIN
DIFF1
SCLK
SDATA
OE [1:0]
Control & Memory
Control
RAM
Rev. 1.1 12/15
Copyright © 2015 by Silicon Laboratories
VDD
NC
Si53152
Si53152
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.1. OE Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.2. OE Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.3. OE Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4.1. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2. Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
5. Pin Descriptions: 24-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Rev. 1.1
3
Si53152
1. Electrical Specifications
Table 1. DC Electrical Specifications
Parameter
3.3 V Operating Voltage
3.3 V Input High Voltage
3.3 V Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Leakage Current
Input Low Leakage Current
3.3 V Output High Voltage
(Single-Ended Outputs)
3.3 V Output Low Voltage
(Single-Ended Outputs)
High-impedance Output
Current
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
Dynamic Supply Current
Symbol
VDD core
V
IH
V
IL
V
IHI2C
V
ILI2C
I
IH
I
IL
V
OH
V
OL
I
OZ
C
IN
C
OUT
L
IN
I
DD_3.3V
All outputs enabled. Differ-
ential clock with 5” traces
and 2 pF load at 100 MHz.
Test Condition
3.3 ± 5%
Control input pins
Control input pins
SDATA, SCLK
SDATA, SCLK
Except internal pull-down
resistors, 0 < V
IN
< V
DD
Except internal pull-up resis-
tors, 0 < V
IN
< V
DD
I
OH
= –1 mA
I
OL
= 1 mA
Min
3.135
2.0
V
SS
– 0.3
2.2
—
—
–5
2.4
—
–10
1.5
—
—
—
Typ
3.3
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
3.465
V
DD
+ 0.3
0.8
—
1.0
5
—
—
0.4
10
5
6
7
20
Unit
V
V
V
V
V
A
A
V
V
µA
pF
pF
nH
mA
4
Rev. 1.1
Si53152
Table 2. AC Electrical Specifications
Parameter
DIFFIN at 0.7 V
Input Frequency Range
Rising and Falling Slew Rates for
Each Clock Output Signal in a
Given Differential Pair
Differential Input High Voltage
Differential Input Low Voltage
Crossing Point Voltage at 0.7 V
Swing
Vcross Variation over all edges
Differential Ringback Voltage
Time before ringback allowed
Absolute Maximum Input
Voltage
Absolute Minimum Input
Voltage
Duty Cycle for Each Clock
Output Signal in a Given
Differential Pair
Rise/Fall Matching
DIFF at 0.7 V
Duty Cycle
Clock Skew
Additive Peak Jitter
Additive PCIe Gen 2
Phase Jitter
Additive PCIe Gen 3
Phase Jitter
T
DC
T
SKEW
Pk-Pk
RMS
GEN2
10 kHz < F < 1.5 MHz
1.5 MHz< F < Nyquist Rate
RMS
GEN3
Includes PLL BW 2–4 MHz
(CDR = 10 MHz)
PCIe Gen 4
Measured at 0 V differential
Measured at 0 V differential
Measured at 0 V differential
Measured at 0 V differential
45
—
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
55
50
10
0.5
0.5
0.10
0.10
50
100
%
ps
ps
ps
ps
ps
ps
ps
ppm
f
in
T
R
/ T
F
Single ended measurement:
V
OL
= 0.175 to V
OH
= 0.525 V
(Averaged)
100
0.6
—
—
210
4
MHz
V/ns
Symbol
Test Condition
Min
Typ
Max
Unit
V
IH
V
IL
V
OX
V
OX
V
RB
T
STABLE
V
MAX
V
MIN
T
DC
Measured at crossing point V
OX
Single-ended measurement
Single-ended measurement
150
—
250
—
–100
500
—
—
—
—
—
—
—
—
–150
550
140
100
—
1.15
—
55
mV
mV
mV
mV
mV
ps
V
V
%
–0.3
45
—
—
T
RFM
Determined as a fraction of
2 x (T
R
– T
F
)/(T
R
+ T
F
)
—
—
20
%
Additive PCIe Gen 4 Phase Jitter RMS
GEN4
Additive Cycle to Cycle Jitter
Long Term Accuracy
T
CCJ
L
ACC
Notes:
1.
Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
2.
Download the Silicon Labs PCIe Clock Jitter Tool at
www.silabs.com/pcie-learningcenter.
Rev. 1.1
5
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