Si50122-A5/A6
C
R YS TA L
- L
ESS
P C I -E
X P R E S S
G
EN
1 , G
EN
2, & G
EN
3
DUAL
O
UTPUT
C
LOCK
G
E NERATOR
Features
Crystal-less clock generator with
integrated CMEMS
PCI-Express Gen 1/2/3 compliant
Two PCIe 100 MHz differential
HCSL outputs
One 25 MHz single-ended
LVCMOS output
Supports Serial (ATA) at
100 MHz
Low power differential output
buffers
No termination resistors required
for differential output clocks
Triangular spread spectrum
profile for maximum EMI
reduction (Si50122-A6)
Industrial Temperature –40 to
85 °C
2.5 V, 3.3 V Power supply
Small package 10-pin TDFN
(2.0x2.5 mm)
Si50122-A5 does not support
spread spectrum outputs
Si50122-A6 supports 0.5% down
spread outputs
Ordering Information:
See page 10
Pin Assignments
Applications
Network Attached Storage
Multi-function Printer
Digital TV
Set top box
Solid State Drives (SSD)
Wireless Access Point
Home Gateway
Digital Video Cameras
VSS
REFOUT
NC
D IF F1
1
2
3
4
5
10
9
VDD
VDD
D IF F2
D IFF2
VSS
Si50122
8
7
6
Description
Si50122-A5/A6 is a high performance, crystal-less PCIe clock generator
that can generate two 100 MHz PCIe clock and one 25 MHz LVCMOS
clock outputs. The clock outputs are compliant to PCIe Gen 1, Gen 2, and
Gen 3 specifications. The ultra-small footprint (2.0x2.5 mm) and industry-
leading low power consumption make Si50122-A5/A6 the ideal clock
solution for consumer and embedded applications where board space is
limited and low power is needed.
D IF F1
Patents pending
Functional Block Diagram
VDD
REFOUT
DIFF1
CMEMS
PLL
(SSC)
Divider
DIFF2
VSS
Rev 0.7 9/14
Copyright © 2014 by Silicon Laboratories
Si50122-A5/A6
Si50122-A5/A6
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
6. Recommended Design Guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Rev 0.7
3
Si50122-A5/A6
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Supply Voltage (3.3 V Supply)
Supply Voltage (2.5 V Supply)
Symbol
V
DD
V
DD
Test Condition
3.3 V ± 10%
2.5 V ± 10%
Min
2.97
2.25
Typ
3.3
2.5
Max
3.63
2.75
Unit
V
V
Table 2. DC Electrical Specifications
Parameter
Operating Voltage
VDD=3.3 V
Operating Voltage
VDD=2.5 V
Operating Supply Current
Symbol
V
DD
V
DD
I
DD
Test Condition
3.3 V ± 10%
2.5 V ± 10%
Full active; 3.3 V ± 10%
Full active; 2.5 V ± 10%
Input Pin Capacitance
Output Pin Capacitance
C
IN
C
OUT
Input Pin Capacitance
Output Pin Capacitance
Min
2.97
2.25
—
—
—
—
Typ
3.30
2.5
20
18
3
—
Max
3.63
2.75
23
21
5
5
Unit
V
V
mA
mA
pF
pF
4
Rev 0.7
Si50122-A5/A6
Table 3. AC Electrical Specifications
Parameter
DIFF Clocks
Duty Cycle
Symbol
T
DC
T
SKEW
F
OUT
F
ACC
t
r/f2
V
OX
V
HIGH
V
LOW
S
RNG
F
MOD
Test Condition
Measured at 0 V differential
Measured at 0 V differential
VDD = 3.3 V
All output clocks
Min
45
—
—
—
0.6
300
—
–0.3
Typ
—
—
100
—
—
—
—
—
—
31.5
Max
55
100
—
100
5.0
550
1.15
—
–0.5
33
Unit
%
ps
MHz
ppm
V/ns
mV
V
V
%
kHz
Skew
Output Frequency
Frequency Accuracy
Slew Rate
Crossing Point Voltage at 0.7 V
Swing
Voltage High
Voltage Low
Spread Range
Modulation Frequency
Measured differentially from
±150 mV
Down Spread, -A6 only
-A6 only
—
30
DIFF Clocks Jitter Parameters, V
DD
= 3.3 V ±10%
PCIe Gen1 Pk-Pk
PCIe Gen2 Phase Jitter
Pk-Pk
GEN1
RMS
GEN2
RMS
GEN3
PCIe Gen 1
10 kHz < F < 1.5 MHz
1.5 MHz < F < Nyquist
PCIe Gen3 Phase Jitter
Includes PLL BW 2-4 MHz,
CDR = 10 MHz
—
—
—
—
20.7
0.8
1.4
0.4
35
2.1
2.2
0.7
ps
ps
ps
ps
DIFF Clocks Jitter Parameters, V
DD
= 2.5 V ±10%
PCIe Gen1 Pk-Pk
PCIe Gen2 Phase Jitter
Pk-Pk
GEN1
RMS
GEN2
RMS
GEN3
PCIe Gen 1
10 kHz < F < 1.5 MHz
1.5 MHz < F < Nyquist
PCIe Gen3 Phase Jitter
25 MHz at 3.3 V
Duty Cycle
—
—
—
—
25
0.9
1.7
0.4
40
2.9
3.0
0.7
ps
ps
ps
ps
Includes PLL BW 2-4 MHz,
CDR = 10 MHz
T
DC
t
r
t
f
T
CCJ
L
ACC
T
STABLE
Measurement at 1.5 V
C
L
= 10 pF, 20% to 80%
C
L
= 10 pF, 20% to 80%
Measurement at 1.5 V
Measured at 1.5 V
45
—
1.2
1.2
55
3.0
3.0
250
50
%
ns
ns
ps
ppm
Output Rise Time
Output Fall Time
Cycle to Cycle Jitter
Long Term Accuracy
Powerup Time
Clock Stabilization from Powerup
—
—
—
—
First power up to first output
—
—
10
ms
Note:
Visit www.pcisig.com for complete PCIe specifications.
Rev 0.7
5
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