155 Mbps ATM SAR Controller

With ABR Support for PCI-based

Networking Applications

IDT77252

x

Full-duplex Segmentation and Reassembly (SAR) at 155

Mbps "wire-speed" (310 Mbps aggregate speed)

Operates with ATM Networks up to 155.52 Mbps

Stand-alone Controller: Embedded Processor not required

Performs ATM Layer Protocol Functions

Supports AAL5, AAL3/4, AAL0 and Raw Cell Formats

Supports Constant Bit Rate (CBR), Variable Bit Rate (VBR),

and Unassigned Bit Rate (UBR), and Available Bit Rate

(ABR) Service Classes

Segments and Reassembles CS-PDUs into Host Memory

Up to 16K Open Transmit Connections

Up to 16K Simultaneous Receive Connections

ABR, VBR, UBR Selectable per VC Time-out

Automatic AAL5 Padding

Four Buffer Pools for Independent or Chained Reassembly

Supports Any Buffer Alignment Condition

Free Buffer Queues Mapped Into PCI Memory Space

Rx FIFO Size (Configurable to 1024 Kbytes)

Configurable Transmit FIFO Depth for Reduced Latency

Supports Big and Little Endian Data Transfers

Null Cell Disable Option During Transmit

NAND Test Mode

RM Cell Handling

UTOPIA Level 1 Interface to PHY

Utility Bus Interface for PHY Management

x

Serial EEPROM Interface

x

EPROM Interface

x

PCI 2.1 Compliant

x

UNI 3.1, TM 4.0 Compliant

x

Meets PCI Bus Power Management and Interface

Specification Revision 1.1

x

Pin Compatible with IDT 77211 SAR

x

Commercial and Industrial Temperature Ranges

x

208-Lead PQFP Package (28 x 28mm)

x

Software Drivers:

– SARWIN 2 Demonstration Program

– NDIS Driver

– Vx Works (3rd party)

– Linux (3rd party)

The IDT77252 NICStAR

™

is a member of IDT's family of products for

Asynchronous Transfer Mode (ATM) networks. The ABR SAR performs

both the ATM Adaptation Layer (AAL) Segmentation and Reassembly

(SAR) function and the ATM layer protocol functions.

A Network Interface Card (NIC) or internetworking product based on

the ABR SAR uses host memory, rather than local memory, to reas-

semble Convergence Sublayer Protocol Data Units (CS-PDUs) from

ATM cell payloads received from the network. When transmitting, as CS-

PDUs become ready, they are queued in host memory and segmented

16K x 32 to 512K x 32

SRAM

PCI BUS

8

EPROM

32

Rx UTOPIA Bus

PCI Interface

8

33MHZ

32

IDT77252

155Mbps

PCI ATM

ABR SAR

155Mbps

PHY

2

Tx UTOPIA Bus

8

Utility Bus

8

80.0MHZ OSC.

EEPROM

4057 drw 01

1 of 17



2001 Integrated Device Technology, Inc.

March 26, 2001

DSC 4057/8

IDT77252

by the ABR SAR into ATM cell payloads. From this, the ABR SAR then creates complete 53-byte ATM cells which are sent through the network. The

ABR SAR's on-chip PCI bus master interface provides efficient, low latency DMA transfers with the host system, while its UTOPIA interface provides

direct connection to PHY components used in 25.6 Mbps to 155 Mbps ATM networks.

The IDT77252 is fabricated using state-of-the-art CMOS technology, providing the highest levels of integration, performance and reliability, with the

low-power consumption characteristics of CMOS.

Transm it

C ontrol

Tx

U topia

Interface

8

/

T x U topia

Bus

32

S R A M IN T E R FA CE

/

SRAM

Bus

PCI Bus

.

32

/

PCI

Interface

Rx

U topia

Interface

8

Receive

C ontrol

8

/

R x U topia

Bus

/

U tility

EE PRO M O U T

E E P R O M IN

4057 drw 02

Vcc

AD(31)

AD(30)

AD(29)

AD(28)

AD(27)

AD(26)

GND

AD(25)

AD(24)

C/BE(3)

IDSEL

AD(23)

AD(22)

GND

AD(21)

Vcc

AD(20)

AD(19)

AD(18)

AD(17)

AD(16)

GND

C/BE(2)

Vcc

FRAME

IRDY

TRDY

DEVSEL

STOP

GND

INTA

Vcc

PERR

SERR

PAR

C/BE(1)

AD(15)

GND

AD(14)

AD(13)

AD(12)

AD(11)

AD(10)

AD(9)

AD(8)

GND

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

208 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

000000009999999999888888888877777777776666666666555

7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7156

155

Index

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

IDT77252 SAR Controller

135

With ABR Support

134

133

208 Pin PQFP

132

Pinout

131

130

PU-208

129

DUI-208

128

127

126

Refer to PSC-4053 for

125

124

detailed package drawing

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

1 1 1 1 1 106

5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 9 9 9 9 9 9 9 9 9 9 0 0 0 0 0 105

34567 890 123 456789 012 345 678901234 56789 012345 67890 1234

Vcc

GND

C/BE(0)

AD(7)

Vcc

AD(6)

AD(5)

AD(4)

GND

SR_A17

AD(3)

AD(2)

AD(1)

AD(0)

GND

SR_A15

SR_WE

SR_A13

SR_A8

SR_A9

SR_A11

SR_OE

SR_A10

SR_CS

SR_A16

GND

SR_A14

Vcc

SR_A12

SR_A7

SR_A6

SR_A5

SR_A4

SR_A3

SR_A2

SR_A1

SR_A0

SR_A18

GND

SR_I/O(0)

SR_I/O(1)

SR_I/O(2)

SR_I/O(3)

SR_I/O(4)

SR_I/O(5)

GND

SR_I/O(6)

SR_I/O(7)

SR_I/O(8)

SR_I/O(9)

SR_I/O(10)

GND

Vcc

REQ

GNT

CLK

RST

GND

NAND_EN

GND

CLK_OUT

Vcc

ADD18_17_EN

GND

NAND_OUT

GND

TXPARITY

PHY_CLK

RXCLK

GND

RXEMPTY/RxCLAV

RXENB

RXSOC

RXDATA(7)

RXDATA(6)

RXDATA(5)

RXDATA(4)

GND

RXDATA(3)

RXDATA(2)

RXDATA(1)

RXDATA(0)

GND

TXCLK

TXFULL/TxCLAV

TXENB

TXSOC

GND

TXDATA(7)

TXDATA(6)

VCC

TXDATA(5)

TXDATA(4)

GND

TXDATA(3)

TXDATA(2)

TXDATA(1)

TXDATA(0)

UTL_CS(1)

UTL_CS(0)

Vcc

GND

PHY_INT

PHY_RST

UTL_ALE

UTL_RD

UTL_WR

GND

UTL_AD(7)

UTL_AD(6)

UTL_AD(5)

UTL_AD(4)

Vcc

UTL_AD(3)

GND

UTL_AD(2)

UTL_AD(1)

UTL_AD(0)

Vcc

SAR_CLK

GND

EEDO

EEDI

EESCLK

EECS

Vcc

E_CE

SR_I/O(31)

SR_I/O(30)

SR_I/O(29)

GND

SR_I/O(28)

SR_I/O(27)

SR_I/O(26)

SR_I/O(25)

SR_I/O(24)

Vcc

SR_I/O(23)

GND

SR_I/O(22)

SR_I/O(21)

SR_I/O(20)

SR_I/O(19)

SR_I/O(18)

SR_I/O(17)

GND

SR_I/O(16)

SR_I/O(15)

SR_I/O(14)

SR_I/O(13)

SR_I/O(12)

SR_I/O(11)

Vcc

4057 drw 03

2 of 17

March 26, 2001

IDT77252

!

1.228 ±0.016 (31.2 ±0.4)

1.10 ±0.004 (28.0 ±0.1)

208

157

1

0.02 ±0.004

(0.5 ±0.1)

Index

156

0.008 ±0.004

(0.2 ±0.1)

52

105

53

104

0.133 ±0.004

(3.37 ±0.1)

0.013 ±0.002

(0.33 ±0.06)

0.024 ±0.008

(0.6 ±0.2)

0.063 (1.6)

4057 drw 04

1

2

3

4

5

6

7

8

9

10

11

12

13

V

CC

AD(31)

AD(30)

AD(29)

AD(28)

AD(27)

AD(26)

GND

AD(25)

AD(24)

C/BE(3)

IDSEL

I

I/O

I

I/O

I

power

PCI

power

PCI

address/data line

bus command

bus ID select

3 of 17

1.10 ±0.004 (28.0 ±0.1)

1.228 ±0.016 (31.2 ±0.4)

March 26, 2001

IDT77252

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

AD(23)

AD(22)

GND

AD(21)

V

CC

AD(20)

AD(19)

AD(18)

AD(17)

AD(16)

GND

C/BE(2)

V

CC

Frame

IRDY

TRDY

DEVSEL

STOP

GND

INTA

V

CC

PERR

SERR

PAR

C/BE(1)

AD(15)

GND

AD(14)

AD(13)

AD(12)

AD(11)

AD(10)

AD(9)

AD(8)

GND

I/O

I

I/O

I

I/O

I

I/O

I

I/O

I

O

I

I/O

O

I/O

I

I/O

I

PCI

power

PCI

power

PCI

power

PCI

power

PCI

power

PCI

power

PCI

power

PCI

power

cycle frame

initiator ready

target ready

bus command

address/data line

target indicating address decode

target requesting master to stop

"interrupt" "A" "request"

data parity error

system error

parity (for AD[0:31] and C/BE[0:3])

bus command

address/data line

4 of 17

March 26, 2001

IDT77252

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

V

CC

GND

C/BE(0)

AD(7)

V

CC

AD(6)

AD(5)

AD(4)

GND

SR_A17

AD(3)

AD(2)

AD(1)

AD(0)

GND

SR_A15

SR_WE

SR_A13

SR_A8

SR_A9

SR_A11

SR_OE

SR_A10

SR_CS

SR_A16

GND

SR_A14

V

CC

SR_A12

SR_A7

SR_A6

SR_A5

SR_A4

SR_A3

SR_A2

SR_A1

SR_A0

SR_A18

GND

I

power

PCI

power

PCI

power

SRAM

PCI

power

SRAM

power

SRAM

power

SRAM

power

Address line

Write enable

Address line

bus command

I/O

I

I/O

I

O

I/O

I

O

I

O

I

O

I

address/data line

Output Enable control

Address line

Chip Select

Address line

5 of 17

March 26, 2001

参数名称	属性值
厂商名称	IDT (Integrated Device Technology)
零件包装代码	QFP
包装说明	FQFP,
针数	208
Reach Compliance Code	unknown
JESD-30 代码	S-PQFP-G208
JESD-609代码	e0
长度	28 mm
功能数量	1
端子数量	208
最高工作温度	70 °C
最低工作温度
封装主体材料	PLASTIC/EPOXY
封装代码	FQFP
封装形状	SQUARE
封装形式	FLATPACK, FINE PITCH
认证状态	Not Qualified
座面最大高度	3.86 mm
标称供电电压	5 V
表面贴装	YES
技术	CMOS
电信集成电路类型	ATM/SONET/SDH SEGMENTATION AND REASSEMBLY DEVICE
温度等级	COMMERCIAL
端子面层	TIN LEAD
端子形式	GULL WING
端子节距	0.5 mm
端子位置	QUAD
宽度	28 mm
Base Number Matches	1

	IDT77252L155PG9	IDT77252L155PG8	IDT77252L155PGI8	IDT77252L155PGI9	IDT77252L155DUI9
描述	ATM Segmentation and Reassembly Device, 1-Func, CMOS, PQFP208, PLASTIC, QFP-208	ATM Segmentation and Reassembly Device, 1-Func, CMOS, PQFP208, PLASTIC, QFP-208	ATM Segmentation and Reassembly Device, 1-Func, CMOS, PQFP208, PLASTIC, QFP-208	ATM Segmentation and Reassembly Device, 1-Func, CMOS, PQFP208, PLASTIC, QFP-208	ATM Segmentation and Reassembly Device, 1-Func, CMOS, PQFP208, PLASTIC, QFP-208
厂商名称	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
零件包装代码	QFP	QFP	QFP	QFP	QFP
包装说明	FQFP,	FQFP,	FQFP,	FQFP,	FQFP,
针数	208	208	208	208	208
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown
JESD-30 代码	S-PQFP-G208	S-PQFP-G208	S-PQFP-G208	S-PQFP-G208	S-PQFP-G208
JESD-609代码	e0	e0	e0	e0	e0
长度	28 mm	28 mm	28 mm	28 mm	28 mm
功能数量	1	1	1	1	1
端子数量	208	208	208	208	208
最高工作温度	70 °C	70 °C	85 °C	85 °C	85 °C
最低工作温度	-	-	-40 °C	-40 °C	-40 °C
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	FQFP	FQFP	FQFP	FQFP	FQFP
封装形状	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
封装形式	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	3.86 mm	3.86 mm	3.86 mm	3.86 mm	3.86 mm
标称供电电压	5 V	5 V	5 V	5 V	5 V
表面贴装	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS
电信集成电路类型	ATM/SONET/SDH SEGMENTATION AND REASSEMBLY DEVICE	ATM/SONET/SDH SEGMENTATION AND REASSEMBLY DEVICE	ATM/SONET/SDH SEGMENTATION AND REASSEMBLY DEVICE	ATM/SONET/SDH SEGMENTATION AND REASSEMBLY DEVICE	ATM/SONET/SDH SEGMENTATION AND REASSEMBLY DEVICE
温度等级	COMMERCIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
端子面层	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD
端子形式	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
端子节距	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm
端子位置	QUAD	QUAD	QUAD	QUAD	QUAD
宽度	28 mm	28 mm	28 mm	28 mm	28 mm
Base Number Matches	1	1	1	1	1

IDT77252L155PG9

IDT77252L155PG9概述

IDT77252L155PG9规格参数

文档预览

IDT77252L155PG9相似产品对比

推荐资源