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COM20022I-3.3V: 产品描述10 mbps arcnet (ansi 878.1) controller with 2kx8 On-chip ram; 文件大小482KB，共83页; 制造商SMC; 官网地址http://www.smc-diodes.com/

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COM20022I-3.3V概述

10 mbps arcnet (ansi 878.1) controller with 2kx8 On-chip ram

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COM20022I 3V

10 Mbps ARCNET (ANSI

878.1) Controller with

2Kx8 On-Board RAM

Datasheet

Product Features

New Features

−

Data Rates up to 10 Mbps

Selectable 8/16 Bit Wide Bus With Data Swapper

Programmable DMA Channel

Programmable Reconfiguration Times

48 Pin TQFP Package; Green, Lead-free package

also available

Eight, 256 Byte Pages Allow Four Pages TX and

RX Plus Scratch-Pad Memory

Next ID Readable

Internal Clock Scaler and Clock Multiplier for

Adjusting Network Speed

Operating Temperature Range of -40

C to +85

Self-Reconfiguration Protocol

Supports up to 255 Nodes

Supports Various Network Topologies (Star,

Tree, Bus...)

CMOS, Single +3V Supply

Duplicate Node ID Detection

Powerful Diagnostics

Receive All Packets Mode

Flexible Media Interface:

−

Traditional Hybrid Interface For Long Distances up

to Four Miles at 2.5Mbps

−

RS485 Differential Driver Interface For Low Cost,

Low Power, High Reliability

Ideal for Industrial/Factory/Building Automation

and Transportation Applications

Deterministic, (ANSI 878.1), Token Passing

ARCNET Protocol

Minimal Microcontroller and Media Interface

Logic Required

Flexible Interface For Use With All

Microcontrollers or Microprocessors

Automatically Detects Type of Microcontroller

Interface

2Kx8 On-Chip Dual Port RAM

Command Chaining for Packet Queuing

Sequential Access to Internal RAM

Software Programmable Node ID

ORDERING INFORMATION

Order Number:

COM20022I3V-HD for 48 Pin TQFP Package

COM20022I3V-HT for 48 Pin TQFP Package (Green, Lead-free)

SMSC COM20022I 3V

Page 1

Revision 02-27-06

DATASHEET

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

Datasheet

80 Arkay Drive

Hauppauge, NY 11788

(631) 435-6000

FAX (631) 273-3123

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete

information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no

responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without

notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does

not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC

or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard

Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors

known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.

SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause

or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further

testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale

Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems

Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES

OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND

ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY

DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR

REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC

OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO

HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH

DAMAGES.

Revision 02-27-06

Page 2

SMSC COM20022I 3V

DATASHEET

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

Datasheet

TABLE OF CONTENTS

Chapter 1

Chapter 2

Chapter 3

Chapter 4

4.1

4.2

4.3

4.4

4.5

4.2.1

General Description ............................................................................................................. 6

Pin Configuration................................................................................................................. 7

Description of Pin Functions ............................................................................................... 8

Protocol Description........................................................................................................... 11

Selecting Clock Frequencies Above 2.5 Mbps .......................................................................................11

Network Protocol ............................................................................................................................... 11

Data Rates......................................................................................................................................... 11

Network Reconfiguration ................................................................................................................... 12

Broadcast Messages......................................................................................................................... 13

Extended Timeout Function .............................................................................................................. 13

4.5.1

4.5.2

4.5.3

Response Time.......................................................................................................................................13

Idle Time.................................................................................................................................................13

Reconfiguration Time..............................................................................................................................13

Invitations To Transmit ...........................................................................................................................14

Free Buffer Enquiries..............................................................................................................................14

Data Packets ..........................................................................................................................................14

Acknowledgements.................................................................................................................................15

Negative Acknowledgements .................................................................................................................15

4.6

Line Protocol ..................................................................................................................................... 13

4.6.1

4.6.2

4.6.3

4.6.4

4.6.5

Chapter 5

5.1

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

System Description............................................................................................................. 16

Selection of 8/16-Bit Access ...................................................................................................................19

DMA Transfers To And From Internal RAM ............................................................................................19

DMA Operation .......................................................................................................................................20

DMA Data Transfer Sequence (I/O to Memory: Read A Packet) ............................................................24

DMA Data Transfer Sequence (Memory to I/O: Write A Packet) ............................................................24

High Speed CPU Bus Timing Support ....................................................................................................24

Traditional Hybrid Interface.....................................................................................................................26

Backplane Configuration.........................................................................................................................26

Differential Driver Configuration..............................................................................................................28

Programmable TXEN Polarity.................................................................................................................28

Microcontroller Interface.................................................................................................................... 16

5.2

Transmission Media Interface ........................................................................................................... 26

5.2.1

5.2.2

5.2.3

5.2.4

Chapter 6

6.1

6.2

6.2.1

6.2.2

6.2.3

6.2.4

6.2.5

6.2.6

6.2.7

6.2.8

6.2.9

6.2.10

6.2.11

6.2.12

6.2.13

6.2.14

6.2.15

Functional Description....................................................................................................... 30

Interrupt Mask Register (IMR) ................................................................................................................32

Data Register..........................................................................................................................................32

Tentative ID Register ..............................................................................................................................32

Node ID Register ....................................................................................................................................33

Next ID Register .....................................................................................................................................33

Status Register .......................................................................................................................................33

Diagnostic Status Register .....................................................................................................................33

Command Register.................................................................................................................................34

Address Pointer Registers ......................................................................................................................34

Configuration Register ........................................................................................................................34

Sub-Address Register .........................................................................................................................34

Setup 1 Register .................................................................................................................................34

Setup 2 Register .................................................................................................................................34

Bus Control Register ...........................................................................................................................35

DMA Count Register ...........................................................................................................................36

Microsequencer................................................................................................................................. 30

Internal Registers .............................................................................................................................. 32

6.3

Internal RAM ..................................................................................................................................... 46

SMSC COM20022I 3V

Page 3

Revision 02-27-06

DATASHEET

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

Datasheet

6.3.1

6.3.2

6.3.3

6.3.4

6.3.5

6.3.6

Sequential Access Memory ....................................................................................................................46

Access Speed.........................................................................................................................................47

Software Interface...................................................................................................................................47

Selecting RAM Page Size.......................................................................................................................47

Transmit Sequence.................................................................................................................................49

Receive Sequence..................................................................................................................................50

6.4

Command Chaining........................................................................................................................... 51

6.4.1

Transmit Command Chaining .................................................................................................................52

6.4.2

Receive Command Chaining ..................................................................................................................52

6.4.3

Reset Details ..........................................................................................................................................53

6.4.3.1

Internal Reset Logic.........................................................................................................................53

6.5

6.6

Initialization Sequence ...................................................................................................................... 53

6.5.1

6.6.1

6.6.2

6.6.3

Bus Determination ..................................................................................................................................53

Normal Results: ......................................................................................................................................55

Abnormal Results: ..................................................................................................................................55

Oscillator.................................................................................................................................................55

Improved Diagnostics........................................................................................................................ 54

Chapter 7

7.1

7.2

Operational Description .................................................................................................... 57

Maximum Guaranteed Ratings* ........................................................................................................ 57

DC Electrical Characteristics............................................................................................................. 57

Chapter 8

Chapter 9

9.1

9.2

Timing Diagrams................................................................................................................ 60

Appendix A ......................................................................................................................... 80

NOSYNC Bit ...................................................................................................................................... 80

EF Bit................................................................................................................................................. 80

Chapter 10

Appendix B ...................................................................................................................... 83

Chapter 11 ................................................................................................................................................. 83

LIST OF FIGURES

Figure 3.1 - COM20022I 3V Operation ........................................................................................................................10

Figure 5.1 - Multiplexed, 8051 - Like Bus Interface with RS-485 Interface .....................................................................17

Figure 5.2 - Non-Multiplexed, 6801-Like Bus Interface with RS-485 Interface ...............................................................18

Figure 5.3 - DREQ Pin First Assertion Timing for all DMA Modes ...............................................................................21

Figure 5.4 - Programmable Burst Mode DMA Transfer (Rough Timing) ......................................................................22

Figure 5.5 - Non-Burst Mode DMA Data Transfer Rough Timing.................................................................................23

Figure 5.6 - Burst Mode DMA Data Transfer Rough Timing ........................................................................................23

Figure 5.7 - High Speed CPU Bus Timing – Intel CPU Mode ......................................................................................25

Figure 5.8 - COM20022I 3V Network Using RS-485 Differential Transceivers...............................................................27

Figure 5.9 - Dipluse Waveform for Data of 1-1-0 ...........................................................................................................27

Figure 5.10 - Internal Block Diagram.............................................................................................................................29

Figure 6.1 - Illustration of the Effect of RTRG Bit on DMA Timing................................................................................35

Figure 6.2 - Sequential Access Operation.....................................................................................................................46

Figure 6.3 - RAM Buffer Packet Configuration ..............................................................................................................49

Figure 6.4 - Command Chaining Status Register Queue...............................................................................................51

Figure 7.1 - AC Measurements ....................................................................................................................................59

Figure 8.1 - Multiplexed Bus, 68XX-Like Control Signals; Read Cycle ........................................................................60

Figure 8.2 - Multiplexed Bus, 80XX-Like Control Signals; Read Cycle ........................................................................61

Figure 8.3 - Multiplexed Bus, 68XX-Like Control Signals; Write Cycle.........................................................................62

Figure 8.4 - Multiplexed Bus, 80XX-Like Control Signals; Write Cycle.........................................................................63

Figure 8.5 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle.................................................................64

Figure 8.6 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle.................................................................65

Figure 8.7 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle.................................................................66

Figure 8.8 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle.................................................................67

Revision 02-27-06

Page 4

SMSC COM20022I 3V

DATASHEET

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

Datasheet

Figure 8.9 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle.................................................................68

Figure 8.10 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle ...............................................................69

Figure 8.11 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle ...............................................................70

Figure 8.12 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle ...............................................................71

Figure 8.13 - Normal Mode Transmit or Receive Timing..............................................................................................72

Figure 8.14 - Backplane Mode Transmit or Receive Timing ........................................................................................73

Figure 8.15 - TTL Input Timing on XTAL1 Pin..............................................................................................................74

Figure 8.16 - Reset and Interrupt Timing .....................................................................................................................74

Figure 8.17 - DMA Timing (Intel Mode 80XX) ..............................................................................................................75

Figure 8.18 - DMA Timing (Motorola Mode 68XX) .......................................................................................................76

Figure 8.19 - 48 Pin TQFP Package Outline ................................................................................................................79

Figure 9.1 - Effect of the EF Bit on the TA/RI Bit..........................................................................................................82

Figure 10.1 - Example of Interface of Circuit Diagram to ISA Bus................................................................................83

LIST OF TABLES

Table 5.1 - Typical Media .............................................................................................................................................29

Table 6.1 - Read Register Summary............................................................................................................................30

Table 6.2 - Data Register at 16 Bit Access ..................................................................................................................31

Table 6.3 - Write Register Summary ............................................................................................................................31

Table 6.4 - Data Register at 16 Bit Address .................................................................................................................32

Table 6.5 - Status Register ...........................................................................................................................................36

Table 6.6 - Diagnostic Status Register..........................................................................................................................37

Table 6.7 - Command Register.....................................................................................................................................38

Table 6.8 - Address Pointer High Register ....................................................................................................................39

Table 6.9 - Address Pointer Low Register.....................................................................................................................39

Table 6.10 - Sub Address Register ...............................................................................................................................40

Table 6.11 - Configuration Register ..............................................................................................................................40

Table 6.12 - Setup 1 Register .......................................................................................................................................42

Table 6.13 - Setup 2 Register .......................................................................................................................................43

Table 6.14 - Bus Control Register.................................................................................................................................44

Table 6.15 - DMA Count Register.................................................................................................................................45

Table 8.1 - DMA Timing................................................................................................................................................77

Table 8.2 - 48 Pin TQFP Package Parameters ............................................................................................................79

SMSC COM20022I 3V

Page 5

Revision 02-27-06

DATASHEET

COM20022I-3.3V相似产品对比

	COM20022I-3.3V	COM20022I-3V
描述	10 mbps arcnet (ansi 878.1) controller with 2kx8 On-chip ram	10 mbps arcnet (ansi 878.1) controller with 2kx8 On-board ram

COM20022I-3.3V

COM20022I-3.3V概述

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