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74AC174MTCX

产品描述IC D-type pos trg sngl 16tssop
产品类别逻辑    逻辑   
文件大小99KB,共9页
制造商Fairchild
官网地址http://www.fairchildsemi.com/
标准
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74AC174MTCX概述

IC D-type pos trg sngl 16tssop

74AC174MTCX规格参数

参数名称属性值
是否Rohs认证符合
厂商名称Fairchild
零件包装代码TSSOP
包装说明4.40 MM, MO-153, TSSOP-16
针数16
Reach Compliance Codeunknown
系列AC
JESD-30 代码R-PDSO-G16
JESD-609代码e3
长度5 mm
负载电容(CL)50 pF
逻辑集成电路类型D FLIP-FLOP
最大频率@ Nom-Sup70000000 Hz
最大I(ol)0.012 A
湿度敏感等级1
位数6
功能数量1
端子数量16
最高工作温度85 °C
最低工作温度-40 °C
输出极性TRUE
封装主体材料PLASTIC/EPOXY
封装代码TSSOP
封装等效代码TSSOP16,.25
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法TAPE AND REEL
峰值回流温度(摄氏度)260
电源3.3/5 V
传播延迟(tpd)12 ns
认证状态Not Qualified
座面最大高度1.2 mm
最大供电电压 (Vsup)6 V
最小供电电压 (Vsup)2 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Matte Tin (Sn)
端子形式GULL WING
端子节距0.65 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
触发器类型POSITIVE EDGE
宽度4.4 mm
最小 fmax100 MHz

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74AC174 • 74ACT174 Hex D-Type Flip-Flop with Master Reset
November 1988
Revised October 2000
74AC174 • 74ACT174
Hex D-Type Flip-Flop with Master Reset
General Description
The AC/ACT174 is a high-speed hex D-type flip-flop. The
device is used primarily as a 6-bit edge-triggered storage
register. The information on the D inputs is transferred to
storage during the LOW-to-HIGH clock transition. The
device has a Master Reset to simultaneously clear all flip-
flops.
Features
s
I
CC
reduced by 50%
s
Outputs source/sink 24 mA
s
ACT174 has TTL-compatible inputs
Ordering Code:
Order Number
74AC174SC
74AC174SJ
74AC174MTC
74AC174PC
74ACT174SC
74ACT174SJ
74ACT174MTC
74ACT174PC
Package Number
M16A
M16D
MTC16
N16E
M16A
M16D
MTC16
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D
0
–D
5
CP
MR
Q
0
–Q
5
Description
Data Inputs
Clock Pulse Input
Master Reset Input
Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation
DS009935
www.fairchildsemi.com

 
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