Using the IDT CMOS oscillator technology, originally developed by
Mobius Microsytems, the 3C02 replaces quartz crystal based
resonators and oscillators with a monolithic CMOS IC at the thinnest
possible form factors without the use of any mechanical frequency
source or PLL. The product is specially designed to work with the
next generation USB 3.0 Super Speed, PCIe
®
Gen1/2 and S-ATA
interface controller ICs and systems.
Features
All-CMOS Temperature Compensated Oscillator
Excellent Frequency Accuracy: +/- 100ppm total
Ultra-low power operation (2mA typical at 1.8V supply)
No quartz or PLL used: very low jitter performance leading to low
link Bit Error Rates (BER)
• Excellent reliability: Shock and vibration resistant
• Many frequencies are supported
• Factory programmable from 6 to 133MHz
•
•
•
•
Ordering Information
3C P 0
1
2
3
C 02 - FFF NSG X 8
4
5
6
7
8 9
Pin Assignment
1) IDT Base Part Number for 100ppm CMOS Oscillator
2) Supply Voltage Configuration
•
•
P: 1.8V to 3.3V continuous operation
0: LVCMOS Output
3) Output Signal Type
4) “C” indicates integrated CMOS Oscillator
5) “XX” is product specific code that indicated product sequence
6) FFF: Factory Programmed Frequency in MHz
7) Package Options*
•
•
•
•
•
•
•
•
1
NSG: 5x3.2, 4-Pin Package
NVG: 2.5x2.0, 4-Pin Package
2
M: SOIC, 8-pin Package
2
“E” -20 to 70
o
C Extended Commercial Temperature Range
“ “ 0 to 70oC Commercial Temperature Range,ie. default is blank
2
“R” -20 to 85oC Restricted Industrial Temperature Range
2
“ “: Shipped in Tube i.e. default is blank
8: Shipped in Tape & Reel
2
3
4
VSS
OUT
VDD
Power
Output
Power
No
1
Name
CE
Type
Input
Pullup
Description
Chip Enable. Internal Pullup. 3C02 is
enabled when HIGH. When LOW, OUT has
a weak pull-down to GND internally
System Ground
Frequency Output
Power Supply. Use a 0.1µF decoupling
capacitor between VDD and VSS
Table 1. Pin Descriptions
8) Temperature Grade
9) Tape & Reel Option
:This product is rated “Green”, please contact factory for environmental compliancy
information
2
: Future product. Not available for design-in. Please contact your IDT representative for
details
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics
or
AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, VDD
Input, V
I
(CE pin)
Output, V
O
(OUT pin)
Storage Temperature
4.6V
Rating
-0.5V to VDD + 0.5V
-0.5V to VDD + 0.5V
-65
o
C to 150
o
C
Electrical Characteristics
5
[3.3V]
VDD=3.0V to 3.6V, T
A
=-20 to 70
o
C unless otherwise noted. Typical values are measured at VDD=3.3V, T
A
=35
o
C
Parameter
ElectroStaticDischa
rge
Supply Voltage
Input LOW level
Input HIGH level
Supply Current
Quiescent Current
Output LOW level
Output HIGH level
Output Frequency
Frequency Stability
Rise Time
Fall Time
Duty Cycle
Symbol
ESD
VDD
V
IL
V
IH
IDD
IDDQ
V
OL
V
OH
F
OUT
F
TOT
RT
FT
DC
Conditions
Human Body Model, tested per JESD D22-A114
Normal Operation
3
CE pin
CE pin
Active supply current, VDD=3.3V, T=35oC, no output load
CE=LOW, output disabled
I
OL
= -4mA
I
OH
= 4mA
Factory Programmable.Contact IDT for frequencies not listed
Total Frequency Stability over temperature,supply
variation,aging (1st year at 35oC),shock&vibration. “E” device
option, over -20 to 70
o
C range
20% to 80% x VDD. Output load (C
L
) =8pF, NSG-option
80% to 20% x VDD. Output load (C
L
) =8pF, NSG-option
Clock output duty cycle. Measured under 80MHz, VDD/2,
C
L
=8pF
Clock output duty cycle. Measured over 80MHz, VDD/2,
C
L
=8pF
Output valid time after VDD meets the specified range&CE
transition
Total RMS Period Jitter (including random and
deterministic)
1,2
The absolute value of max change in the periods of any 2
adjacent cycles
1,2,4
1MHz offset from carrier
1,2
Min
4000
3.0
-0.3
VDD*0.7
Typ
Max
Units
V
3.3
2.5
0.2
VDD-0.5
12,48,75,125
3.6
VDD*0.3
VDD+0.3
3.0
1
0.5
V
V
V
mA
µA
V
V
MHz
ppm
ns
ns
%
%
µs
ps
RMS
+100
1.9
1.9
45
40
50
100
3.5
50
-140
-135
55
60
400
Power-up time
Period Jitter
Cycle-cycle Jitter
Phase Noise
t
on
PJ
RMS
CJ
PN
ps
dBc/Hz
Notes 1. Measured with a 50Ω to GND termination
2: Measured at 48MHz output frequency
3. The 3C02 will support continuous VDD operation from 1.62 to 3.6V. The device can be powered up with a supply voltage at any of the 3 main supply rails of 1.8V, 2.5V or 3.3V.
4. Measured over 1000 cycles per JEDEC standard 65
5. Electrical parameters are guaranteed by design and characterization over the specified ambient operating temperature range, which is established when the device is mounted in a
test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions.
C unless otherwise noted. Typical values are measured at VDD=2.5V, T
A
=35
o
C
Parameter
ElectroStaticDischa
rge
Supply Voltage
Input LOW level
Input HIGH level
Supply Current
Quiescent Current
Output LOW level
Output HIGH level
Output Frequency
Frequency Stability
Rise Time
Fall Time
Duty Cycle
Symbol
ESD
VDD
V
IL
V
IH
IDD
IDDQ
V
OL
V
OH
F
OUT
F
TOT
RT
FT
DC
Conditions
Human Body Model, tested per JESD D22-A114
Normal Operation
3
CE pin
CE pin
Active supply current, VDD=2.5V, T=35oC, no output load
CE=LOW, output disabled
I
OL
= -3mA
I
OH
= 3mA
Factory Programmable.Contact IDT for frequencies not listed
Total Frequency Stability over temperature,supply
variation,aging (1st year at 35oC),shock&vibration. “E” device
option, over -20 to 70
o
C range
20% to 80% x VDD. Output load (C
L
) =7pF, NSG-option
80% to 20% x VDD. Output load (C
L
) =7pF, NSG-option
Clock output duty cycle. Measured under 100MHz at VDD/2,
C
L
=7pF
Clock output duty cycle. Measured over 100MHz at VDD/2,
C
L
=7pF
Output valid time after VDD meets the specified range&CE
transition
Total RMS Period Jitter (including random and
deterministic)
1,2
The absolute value of max change in the periods of any 2
adjacent cycles
1,2,4
1MHz offset from carrier
1,2
Min
4000
2.25
-0.3
VDD*0.7
Typ
Max
Units
V
2.5
2.25
0.2
VDD-0.4
12,48,75,125
2.75
VDD*0.3
VDD+0.3
2.75
1
0.4
V
V
V
mA
µA
V
V
MHz
ppm
ns
ns
%
%
µs
ps
RMS
+100
2.3
2.3
45
40
50
100
3.5
50
-140
-135
55
60
400
Power-up time
Period Jitter
Cycle-cycle Jitter
Phase Noise
t
on
PJ
RMS
CJ
PN
ps
dBc/Hz
Notes 1. Measured with a 50Ω to GND termination
2: Measured at 48MHz output frequency
3. The 3C02 will support continuous VDD operation from 1.62 to 3.6V. The device can be powered up with a supply voltage at any of the 3 main supply rails of 1.8V, 2.5V or 3.3V.
4. Measured over 1000 cycles per JEDEC standard 65
5. Electrical parameters are guaranteed by design and characterization over the specified ambient operating temperature range, which is established when the device is mounted in a
test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions.
C unless otherwise noted. Typical values are measured at VDD=1.8V, T
A
=35
o
C
Parameter
ElectroStaticDischa
rge
Supply Voltage
Input LOW level
Input HIGH level
Supply Current
Quiescent Current
Output LOW level
Output HIGH level
Output Frequency
Frequency Stability
Rise Time
Fall Time
Duty Cycle
Power-up time
Period Jitter
Cycle-cycle Jitter
Phase Noise
Symbol
ESD
VDD
V
IL
V
IH
IDD
IDDQ
V
OL
V
OH
F
OUT
F
TOT
RT
FT
DC
t
on
PJ
RMS
CJ
PN
Conditions
Human Body Model, tested per JESD D22-A114
Normal Operation
3
CE pin
CE pin
Active supply current, VDD=1.8V, T=35oC, no output load
CE=LOW, output disabled
I
OL
= -1.8mA
I
OH
= 1.8mA
Factory Programmable.Contact IDT for frequencies not listed
Total Frequency Stability over temperature,supply
variation,aging (1st year at 35oC),shock&vibration. “E” device
option, over -20 to 70
o
C range
20% to 80% x VDD. Output load (C
L
) =4pF, NSG-option
80% to 20% x VDD. Output load (C
L
) =4pF, NSG-option
Clock output duty cycle. Measured at VDD/2, C
L
=4pF
Output valid time after VDD meets the specified range&CE
transition
Total RMS Period Jitter (including random and
deterministic)
1,2
The absolute value of max change in the periods of any 2
adjacent cycles
1,2,4
1MHz offset from carrier
1,2
Min
4000
1.62
-0.3
VDD*0.7
Typ
Max
Units
V
1.8
2.0
0.2
VDD-0.3
12,48,75,125
1.98
VDD*0.3
VDD+0.3
2.5
1
0.3
V
V
V
mA
µA
V
V
MHz
ppm
ns
ns
%
µs
ps
RMS
+100
2.75
2.75
55
100
3.5
50
-140
-135
400
45
50
ps
dBc/Hz
Notes 1. Measured with a 50Ω to GND termination
2: Measured at 48MHz output frequency
3. The 3C02 will support continuous VDD operation from 1.62 to 3.6V. The device can be powered up with a supply voltage at any of the 3 main supply rails of 1.8V, 2.5V or 3.3V.
4. Measured over 1000 cycles per JEDEC standard 65
5. Electrical parameters are guaranteed by design and characterization over the specified ambient operating temperature range, which is established when the device is mounted in a
test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions.
Application Diagram
Below is a representative application diagram to evaluate the 3C02. For 50Ohm terminated measurements, a balun is necessary to provide
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