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IDT74FCT652ATSO8

产品描述Registered Bus Transceiver, FCT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO24, SOIC-24
产品类别逻辑    逻辑   
文件大小80KB,共9页
制造商IDT (Integrated Device Technology)
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IDT74FCT652ATSO8概述

Registered Bus Transceiver, FCT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO24, SOIC-24

IDT74FCT652ATSO8规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称IDT (Integrated Device Technology)
零件包装代码SOIC
包装说明SOIC-24
针数24
Reach Compliance Codenot_compliant
其他特性SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED/REAL TIME DATA
控制类型INDEPENDENT CONTROL
计数方向BIDIRECTIONAL
系列FCT
JESD-30 代码R-PDSO-G24
JESD-609代码e0
长度15.4 mm
负载电容(CL)50 pF
逻辑集成电路类型REGISTERED BUS TRANSCEIVER
最大I(ol)0.064 A
湿度敏感等级1
位数8
功能数量1
端口数量2
端子数量24
最高工作温度85 °C
最低工作温度-40 °C
输出特性3-STATE
输出极性TRUE
封装主体材料PLASTIC/EPOXY
封装代码SOP
封装等效代码SOP24,.4
封装形状RECTANGULAR
封装形式SMALL OUTLINE
包装方法TAPE AND REEL
峰值回流温度(摄氏度)NOT SPECIFIED
电源5 V
Prop。Delay @ Nom-Sup6.3 ns
传播延迟(tpd)6.3 ns
认证状态Not Qualified
座面最大高度2.65 mm
最大供电电压 (Vsup)5.25 V
最小供电电压 (Vsup)4.75 V
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Tin/Lead (Sn/Pb)
端子形式GULL WING
端子节距1.27 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
翻译N/A
触发器类型POSITIVE EDGE
宽度7.5 mm
Base Number Matches1

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IDT74FCT652AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE)
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS OCTAL
TRANSCEIVER/
REGISTER (3-STATE)
FEATURES:
IDT74FCT652AT/CT
A and C grades
Low input and output leakage
1µA (max.)
CMOS power levels
True TTL input and output compatibility:
– V
OH
= 3.3V (typ.)
– V
OL
= 0.3V (typ.)
High Drive outputs (-15mA I
OH
, 64mA I
OL
)
Meets or exceeds JEDEC standard 18 specifications
Power off disable outputs permit "live insertion"
Available in SOIC and QSOP packages
DESCRIPTION:
The FCT652T consists of a bus transceiver with 3-state D-type flip-flops
and control circuitry arranged for multiplexed transmission of data directly
from the data bus or from the internal storage registers. The FCT652T
utilizes GAB and
GBA
signals to control the transceiver functions.
SAB and SBA control pins are provided to select either real- time or stored
data transfer. The circuitry used for select control will eliminate the typical
decoding glitch that occurs in a multiplexer during the transition between
stored and real-time data. A low input level selects real-time data and a high
selects stored data.
Data on the A or B data bus, or both, can be stored in the internal D flip-
flops by low-to-high transitions at the appropriate clock pins (CPAB or
CPBA), regardless of the select or enable control pins.
FUNCTIONAL BLOCK DIAGRAM
GBA
GAB
CPBA
SBA
CPAB
SAB
B REG
ONE OF EIGHT CHANNELS
1D
C1
A1
A REG
1D
C1
B1
TO SEVEN OTHER CHANN ELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
JANUARY
2004
DSC-5508/4
© 2004 Integrated Device Technology, Inc.

 
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