Freescale Semiconductor
Data Sheet: Technical Data
Document Number: PXR40
Rev. 1, 09/2011
PXR40
PXR40 Microcontroller Data
Sheet
TEPBGA–416
27mm x 27mm
• Dual issue, 32-bit CPU core complex (e200z7)
– Compliant with the Power Architecture embedded
category
– 16 KB I-Cache and 16 KB D-Cache
– Includes an instruction set enhancement allowing
variable length encoding (VLE), optional encoding of
mixed 16-bit and 32-bit instructions, for code size
footprint reduction
– Includes signal processing extension (SPE2) instruction
support for digital signal processing (DSP) and
single-precision floating point operations
• 4 MB on-chip flash
– Supports read during program and erase operations, and
multiple blocks allowing EEPROM emulation
• 256 KB on-chip general-purpose SRAM including 32 KB
of standby RAM
• Two direct memory access controller (eDMA2) blocks
– One supporting 64 channels
– One supporting 32 channels
• Interrupt controller (INTC)
• Frequency modulated phase-locked loop (FMPLL)
• Crossbar switch architecture for concurrent access to
peripherals, flash, or RAM from multiple bus masters
• External bus interface (EBI) for calibration and application
development (not available on all packages)
• System integration unit (SIU)
• Error correction status module (ECSM)
• Boot assist module (BAM) supports serial bootload via
CAN or SCI
• Two second-generation enhanced time processor units
(eTPU2) that share code and data RAM.
– 32 standard channels per eTPU2
– 24 KB code RAM
– 6 KB parameter (data) RAM
• Enhanced modular input output system supporting 32
unified channels (eMIOS) with each channel capable of
•
•
•
•
•
•
•
•
single action, double action, pulse width modulation
(PWM) and modulus counter operation
Four enhanced queued analog-to-digital converters
(eQADC)
– Support for 64 analog channels
– Includes one absolute reference ADC channel
– Includes eight decimation filters
Four deserial serial peripheral interface (SPI) modules
Three enhanced serial communication interface (UART)
modules
Four controller area network (CAN) modules
Dual-channel FlexRay controller
Nexus development interface (NDI) per IEEE-ISTO
5001-2003/5001-2008 standard
Device and board test support per Joint Test Action Group
(JTAG) (IEEE 1149.1)
On-chip voltage regulator controller regulates supply
voltage down to 1.2 V for core logic
© Freescale Semiconductor, Inc., 2011. All rights reserved.
Table of Contents
1
2
3
4
5
PXR40 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
PXR40 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3.1 416-ball TEPBGA pin assignments. . . . . . . . . . . . . . . . .6
Signal properties and muxing . . . . . . . . . . . . . . . . . . . . . . . . .11
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
5.1 Maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
5.2 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .53
5.2.1 General notes for specifications at maximum junction
temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.3 EMI (Electromagnetic Interference) characteristics . . .55
5.4 ESD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .56
5.5 PMC/POR/LVI electrical specifications . . . . . . . . . . . . .56
5.6 Power up/down sequencing . . . . . . . . . . . . . . . . . . . . .59
5.6.1 Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
5.6.2 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
5.6.3 Power sequencing and POR dependent on V
DDA
60
5.7 DC electrical specifications . . . . . . . . . . . . . . . . . . . . . .61
5.7.1 I/O pad current specifications . . . . . . . . . . . . . .64
5.7.2 I/O pad V
DD33
current specifications . . . . . . . . .64
5.7.3 LVDS pad specifications . . . . . . . . . . . . . . . . . .65
5.8 Oscillator and FMPLL electrical characteristics . . . . . .66
eQADC electrical characteristics . . . . . . . . . . . . . . . . .
5.9.1 ADC internal resource measurements . . . . . . .
5.10 C90 flash memory electrical characteristics . . . . . . . .
5.11 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.11.1 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.11.2 Pad AC specifications. . . . . . . . . . . . . . . . . . . .
5.12 AC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.12.1 Generic timing diagrams . . . . . . . . . . . . . . . . .
5.12.2 Reset and configuration pin timing . . . . . . . . . .
5.12.3 IEEE 1149.1 interface timing . . . . . . . . . . . . . .
5.12.4 Nexus timing. . . . . . . . . . . . . . . . . . . . . . . . . . .
5.12.5 External Bus Interface (EBI) timing . . . . . . . . .
5.12.6 External interrupt timing (IRQ pin) . . . . . . . . . .
5.12.7 eTPU timing . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.12.8 eMIOS timing . . . . . . . . . . . . . . . . . . . . . . . . . .
5.12.9 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 416-pin package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9
68
69
71
73
73
74
77
77
78
78
81
84
88
88
89
90
96
96
97
97
99
99
6
7
8
9
PXR40 Microcontroller Data Sheet, Rev. 1
2
Freescale Semiconductor
PXR40 features
1
PXR40 features
Table 1. PXR40 feature set
Feature
Core
SIMD
VLE
Cache
Non-maskable interrupt (NMI)
MMU
MPU
XBAR
Windowing software watchdog
Nexus
SRAM
Flash
Flash fetch accelerator
External bus
Calibration bus
DMA
DMA Nexus
Serial
UART_A
UART_B
UART_C
Microsecond bus uplink
CAN
CAN_A
CAN_B
CAN_C
CAN_D
CAN_E
SPI
SPI_A
SPI_B
SPI_C
SPI_D
FlexRay
Ethernet
System timers
PXR40
e200z7
Yes
Yes
32 KB
(16 KB Instruction/16 KB Data)
NMI & Critical Interrupt
64 entry
Yes
5×5
Yes
3+
256 KB
4 MB
4 × 256 bit
(first 1 MB of memory is 4 × 128; last 3 MB are 4 × 256)
Yes
16 bit non-muxed
32 bit muxed
96 channel
Class 3
3
Yes
Yes
Yes
Yes
4
64 message buffers
64 message buffers
64 message buffers
64 message buffers
No
4
Yes
Yes
Yes
Yes
Yes
No
4 PIT chan
4 SWT
1 Watchdog
32 channel
64 channel
Yes (eTPU2)
Yes (eTPU2)
Table 1
displays the PXR40 feature set.
eMIOS
eTPU
eTPU_A
eTPU_B
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
3
PXR40 features
Table 1. PXR40 feature set (continued)
Feature
Code memory
Data memory
Interrupt controller
ADC
eQADC_A
eQADC_B
Temperature sensor
Variable gain amp.
Decimation filter
Sensor diagnostics
PLL
VRC
Supplies
Low Power Modes
24 KB
6 KB
448
64 channel
Yes
Yes
Yes
Yes
Yes (8 on eQADC_B)
Yes
FM
Yes
5V
Stop Mode
Slow Mode
PXR40
Note:
3.3 V is required for certain IO segments only during debug/development (e.g., Nexus 3 trace and bus)
PXR40 Microcontroller Data Sheet, Rev. 1
4
Freescale Semiconductor
PXR40 block diagram
2
PXR40 block diagram
PXR40 Block Diagram
System
Integration
SPE2
Osc/PLL
Interrupt
Controller
2 x eDMA
64- and
32-ch
e200z7
Superscalar
CPU
FlexRay™
Controller
Data and Instruction System
Debug
JTAG
Nexus
IEEE
ISTO
5001™-2003
Figure 1
shows a top-level block diagram of the PXR40 microcontrollers.
Crossbar Switch (XBAR)
Memory Protection Unit (MPU)
PBRIDGE A
4 MB
Flash
w/ECC
256 KB
SRAM
w/ECC
(32 KB S/B)
PBRIDGE B
Boot Assist
Module
(BAM)
SIU
Main Memory System
Timed I/O System
6K
Data
24K
Code
RAM
Communications
eMIOS
32-ch
eTPU2
32-ch
eTPU2
32-ch
4x
CAN
3x
UART/
LIN
4x
SPI
4x
Dec
Fil
64-ch
QUAD
ADCi
ADC
– Analog-to-digital converter
ADCi
– ADC interface
AIPS
– Peripheral I/O bridge
AMux
– Analog multiplexer
CAN
– Controller area network
DECFIL–
Decimation filter
EBI
– External bus interface
ECSM
– Error correction status module
eDMA2
– Enhanced direct memory access
eMIOS
– Enhanced modular I/O system
eQADC
– Enhanced queued A/D converter module
eTPU2
– Enhanced time processing unit 2
MMU
MPU
PBRIDGE
S/B
SIU
SPE2
SPI
SRAM
UART/LIN
VLE
– Memory management unit
– Memory protection unit
– Peripheral I/O bridge
– Stand-by
– System integration unit
– Signal processing engine 2
– Serial peripheral interface controller
– General-purpose static RAM
– Universal asynchronous receiver/transmitter/
local interconnect network
– Variable length instruction encoding
Figure 1. Block diagram
PXR40 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
5
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