19-4978; Rev 0; 10/09
EVALUATION KIT AVAILABLE
Low-Jitter, Precision Clock
Generator with Three Outputs
General Description
The MAX3625B is a low-jitter, precision clock generator
optimized for networking applications. The device inte-
grates a crystal oscillator and a phase-locked loop (PLL)
clock multiplier to generate high-frequency clock outputs
for Ethernet, 10G Fibre Channel, and other networking
applications.
This proprietary PLL design features ultra-low jitter and
excellent power-supply noise rejection, minimizing design
risk for network equipment.
The MAX3625B has three LVPECL outputs. Selectable
output dividers and a selectable feedback divider allow a
range of output frequencies.
Features
♦
Crystal Oscillator Interface: 24.8MHz to 27MHz
♦
CMOS Input: Up to 320MHz
♦
Output Frequencies
Ethernet: 62.5MHz, 125MHz, 156.25MHz, 312.5MHz
10G Fibre Channel: 159.375MHz, 318.75MHz
♦
Low Jitter
0.14ps
RMS
(1.875MHz to 20MHz)
0.36ps
RMS
(12kHz to 20MHz)
♦
Excellent Power-Supply Noise Rejection
♦
No External Loop Filter Capacitor Required
MAX3625B
Applications
Ethernet Networking Equipment
Fibre Channel Storage Area Network
Typical Application Circuit appears at end of data sheet.
PART
MAX3625BEUG+
Ordering Information
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
24 TSSOP-EP*
+Denotes
a lead(Pb)-free/RoHS-compliant package.
*EP
= Exposed pad.
Block Diagram
IN_SEL
MR
BYPASS
SELA[1:0]
SELA[1:0]
SELB[1:0]
FB_SEL
BYPASS
QA_OE
RESET LOGIC/POR
RESET
DIVIDER
NA
LVPECL
BUFFER
QA
QA
RESET
LVCMOS
REF_IN
27pF
X_IN
CRYSTAL
OSCILLATOR
X_OUT
33pF
DIVIDERS:
M = 24, 25
NA = 10, 2, 4, 5
NB = 10, 2, 4, 5
LVPECL
BUFFER
QB0
QB0
DIVIDER
M
DIVIDER
NB
1
0
PFD
FILTER
RESET
620MHz TO 648MHz
VCO
1
RESET
LVPECL
BUFFER
QB1
QB1
QB_OE
0
MAX3625B
FB_SEL
SELB[1:0]
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Low-Jitter, Precision Clock
Generator with Three Outputs
MAX3625B
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range V
CC
, V
CCA
,
V
CCO_A
, V
CCO_B
..............................................-0.3V to +4.0V
Voltage Range at REF_IN, IN_SEL,
FB_SEL, SELA[1:0], SELB[1:0],
QA_OE, QB_OE, MR,
BYPASS
..............-0.3V to (V
CC
+ 0.3V)
Voltage Range at X_IN ..........................................-0.3V to +1.2V
Voltage Range at X_OUT ............................-0.3V to (V
CC
- 0.6V)
Current into QA,
QA,
QB0,
QB0,
QB1,
QB1
.....................-56mA
Continuous Power Dissipation (T
A
= +70°C)
24-Pin TSSOP (derate 26.7mW/°C above +70°C) ..2133.3mW
Operating Junction Temperature Range ...........-55°C to +150°C
Storage Temperature Range .............................-65°C to +160°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless other-
wise noted.) (Notes 1, 2)
PARAMETER
Power-Supply Current (Note 3)
SYMBOL
I
CC
IN_SEL = high
IN_SEL = low
CONDITIONS
MIN
TYP
72
74
MAX
98
UNITS
mA
CONTROL INPUT CHARACTERISTICS
(SELA[1:0], SELB[1:0], FB_SEL, IN_SEL, QA_OE, QB_OE, MR,
BYPASS
Pins)
Input Capacitance
Input Pulldown Resistor
Input Logic Bias Resistor
Input Pullup Resistor
C
IN
R
PULLDOWN
Pins MR, FB_SEL
R
BIAS
R
PULLUP
Pins SELA[1:0], SELB[1:0]
Pins QA_OE, QB_OE, IN_SEL,
BYPASS
V
CC
-
1.18
V
CC
-
1.90
(Note 2)
20% to 80% (Note 2)
PLL enabled
PLL bypassed (Note 4)
0.6
200
48
45
2
75
50
75
V
CC
-
0.98
V
CC
-
1.7
0.72
350
50
50
V
CC
-
0.83
V
CC
-
1.55
0.9
600
52
55
pF
k
k
k
LVPECL OUTPUTS (QA,
QA,
QB0,
QB0,
QB1,
QB1
Pins)
Output High Voltage
Output Low Voltage
Peak-to-Peak Output-Voltage
Swing (Single-Ended)
Clock Output Rise/Fall Time
Output Duty-Cycle Distortion
V
OH
V
OL
V
V
V
P-P
ps
%
LVCMOS/LVTTL INPUTS
(SELA[1:0], SELB[1:0], FB_SEL, IN_SEL, QA_OE, QB_OE, MR,
BYPASS
Pins)
Input-Voltage High
Input-Voltage Low
Input High Current
Input Low Current
V
IH
V
IL
I
IH
I
IL
V
IN
= V
CC
V
IN
= 0V
-80
2.0
0.8
80
V
V
μA
μA
2
_______________________________________________________________________________________
Low-Jitter, Precision Clock
Generator with Three Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless other-
wise noted.) (Notes 1, 2)
PARAMETER
SYMBOL
PLL enabled
PLL bypassed
V
IH
V
IL
I
IH
I
IL
V
IN
= V
CC
V
IN
= 0V
PLL enabled
-240
30
2.5
620
RJ
RMS
12kHz to 20MHz
1.875MHz to 20MHz
(Notes 6, 7, 8)
(Note 9)
0.36
0.14
-60
5.6
-70
Between any output pair
f = 1kHz
Clock Output SSB Phase Noise
at 125MHz (Note 10)
f = 10kHz
f = 100kHz
f = 1MHz
f > 10MHz
5
-124
-127
-131
-145
-153
dBc/Hz
648
1.0
70
2.0
0.8
240
CONDITIONS
MIN
24.8
TYP
MAX
27.0
320
UNITS
MAX3625B
REF_IN SPECIFICATIONS (Input DC- or AC-Coupled)
Reference Clock Frequency
Input-Voltage High
Input-Voltage Low
Input High Current
Input Low Current
Reference Clock Duty Cycle
Input Capacitance
CLOCK OUTPUT AC SPECIFICATIONS
VCO Frequency Range
Random Jitter (Note 5)
Spurs Induced by Power-Supply
Noise
Deterministic Jitter Induced by
Power-Supply Noise
Nonharmonic and Subharmonic
Spurs
Output Skew
MHz
ps
RMS
dBc
ps
P-P
dBc
ps
MHz
V
V
μA
μA
%
pF
A series resistor of up to 10.5Ω is allowed between V
CC
and V
CCA
for filtering supply noise when system power-supply
tolerance is V
CC
= 3.3V ±5%. See Figure 1.
Note 2:
LVPECL outputs guaranteed up to 320MHz.
Note 3:
All outputs enabled and unloaded.
Note 4:
Measured with a crystal (see Table 4) or an AC-coupled, 50% duty-cycle signal on REF_IN.
Note 5:
Measured with crystal source, see Table 4.
Note 6:
Measured using setup shown in Figure 1.
Note 7:
Measured with 40mV
P-P
, 100kHz sinusoidal signal on the supply.
Note 8:
Measured at 156.25MHz output.
Note 9:
Calculated based on measured spurs induced by power-supply noise (refer to Application Note 4461:
HFAN-04.5.5:
Characterizing Power-Supply Noise Rejection in PLL Clock Synthesizers).
Note 10:
Measured with 25MHz crystal or 25MHz reference clock at REF_IN with a slew rate of 0.5V/ns or greater.
Note 1:
_______________________________________________________________________________________
3
Low-Jitter, Precision Clock
Generator with Three Outputs
MAX3625B
Typical Operating Characteristics
(Typical values are at V
CC
= +3.3V, T
A
= +25°C, crystal frequency = 25MHz.)
SUPPLY CURRENT
vs. TEMPERATURE
225
200
SUPPLY CURRENT (mA)
175
150
125
100
75
50
25
0
-40
-15
10
35
60
85
1ns/div
AMBIENT TEMPERATURE (°C)
ALL OUTPUTS ACTIVE AND UNTERMINATED
ALL OUTPUTS ACTIVE AND TERMINATED
MAX3625B toc01
DIFFERENTIAL OUTPUT WAVEFORM
AT 156.25MHz
MAX3625B toc02
PHASE NOISE AT 312.5MHz
CLOCK FREQUENCY
-90
-100
-110
-120
-130
-140
-150
-160
0.1
1
10
100
1000 10,000 100,000
OFFSET FREQUENCY (kHz)
MAX3625B toc03
250
-80
NOISE POWER DENSITY (dBc/Hz)
AMPLITUDE (200mv/div)
PHASE NOISE AT 125MHz
CLOCK FREQUENCY
MAX3625B toc04
PHASE NOISE AT 156.25MHz
CLOCK FREQUENCY
MAX3625B toc05
SPURS INDUCED BY POWER-SUPPLY NOISE
vs. NOISE FREQUENCY
-10
-20
SPUR AMPLITUDE (dBc)
-30
-40
-50
-60
-70
-80
-90
-100
f
C
= 156.25MHz
NOISE AMPLITUDE = 40mV
P-P
MAX3625B toc06
-80
NOISE POWER DENSITY (dBc/Hz)
-90
-100
-110
-120
-130
-140
-150
-160
0.1
1
10
100
-80
-90
NOISE POWER DENSITY (dBc/Hz)
-100
-110
-120
-130
-140
-150
-160
0
1000 10,000 100,000
0.1
1
10
100
1000 10,000 100,000
10
100
1000
10,000
OFFSET FREQUENCY (kHz)
OFFSET FREQUENCY (kHz)
NOISE FREQUENCY (kHz)
4
_______________________________________________________________________________________
Low-Jitter, Precision Clock
Generator with Three Outputs
Pin Configuration
TOP VIEW
V
CCO_B
REF_IN
IN_SEL
X_OUT
SELB1
QB1
SELA1
X_IN
GND
QB0
QB0
QB1
MAX3625B
24 23 22 21 20 19 18 17 16 15 14 13
MAX3625B
*EP
+
1
SELB0
2
BYPASS
3
MR
4
V
CCO_A
5
QA
6
QA
7
QB_OE
8
QA_OE
9
FB_SEL
10 11 12
V
CCA
V
CC
SELA0
TSSOP
*EXPOSED PAD MUST BE SOLDERED TO GROUND FOR PROPER
THERMAL AND ELECTRICAL OPERATION.
Pin Description
PIN
1, 24
NAME
SELB0,
SELB1
BYPASS
FUNCTION
LVCMOS/LVTTL Inputs. Control NB divider setting. Has 50k
information.
input impedance. See Table 2 for more
2
LVCMOS/LVTTL Input (Active Low). Connect low to bypass the internal PLL. Connect high or leave
open for normal operation. When in bypass mode the output dividers are set to divide by 1. Has
internal 75k pullup to V
CC
.
LVCMOS/LVTTL Input. Master reset input. Pulse high for > 1μs to reset all dividers. Has internal 75k
pulldown to GND. Not required for normal operation.
Power Supply for QA Clock Output. Connect to +3.3V.
Noninverting Clock Output, LVPECL
Inverting Clock Output, LVPECL
LVCMOS/LVTTL Input. Enables/disables QB clock outputs. Connect pin high or leave open to enable
LVPECL clock outputs QB0 and QB1. Connect low to set QB0 and QB1 to a logic 0. Has internal 75k
pullup to V
CC
.
LVCMOS/LVTTL Input. Enables/disables the QA clock output. Connect high or leave open to enable the
LVPECL clock output QA. Connect low to set QA to a logic 0. Has internal 75k pullup to V
CC
.
LVCMOS/LVTTL Input. Controls M divider setting. See Table 3 for more information. Has internal 75k
pulldown to GND.
3
4
5
6
7
MR
V
CCO_A
QA
QA
QB_OE
8
9
QA_OE
FB_SEL
_______________________________________________________________________________________
5
FPGA/CPLD
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