MC14066B
Quad Analog Switch/Quad
Multiplexer
The MC14066B consists of four independent switches capable of
controlling either digital or analog signals. This quad bilateral switch
is useful in signal gating, chopper, modulator, demodulator and
CMOS logic implementation.
The MC14066B is designed to be pin−for−pin compatible with the
MC14016B, but has much lower ON resistance. Input voltage swings
as large as the full supply voltage can be controlled via each
independent control input.
Features
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•
•
•
•
•
•
•
Triple Diode Protection on All Control Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Linearized Transfer Characteristics
Low Noise − 12 nV/√Cycle, f
≥
1.0 kHz typical
Pin−for−Pin Replacement for CD4016, CD4016, MC14016B
For Lower R
ON
, Use The HC4066 High−Speed CMOS Device
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•
These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS
(Voltages Referenced to V
SS
)
Symbol
V
DD
V
in
, V
out
I
in
I
SW
P
D
T
A
T
stg
T
L
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input Current (DC or Transient)
per Control Pin
Switch Through Current
Power Dissipation, per Package
(Note 1)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8−Second Soldering)
Value
−0.5 to +18.0
−0.5 to V
DD
+ 0.5
±10
±25
500
−55 to +125
−65 to +150
260
Unit
V
V
mA
SOIC−14
D SUFFIX
CASE 751A
SOEIAJ−14
F SUFFIX
CASE 965
TSSOP−14
DT SUFFIX
CASE 948G
PIN ASSIGNMENT
IN 1
OUT 1
OUT 2
IN 2
CONTROL 2
CONTROL 3
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
CONTROL 1
CONTROL 4
IN 4
OUT 4
OUT 3
IN 3
MARKING DIAGRAMS
14
14066BG
AWLYWW
1
1
SOIC−14
14
SOEIAJ−14
14
MC14066B
ALYWG
mA
mW
°C
°C
°C
14
066B
ALYWG
G
1
TSSOP−14
A
WL, L
YY, Y
WW, W
G or
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
≤
(V
in
or V
out
)
≤
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 10
Publication Order Number:
MC14066B/D
MC14066B
ELECTRICAL CHARACTERISTICS
−55_C
Characteristic
Symbol
V
DD
—
5.0
10
15
Control Inputs:
V
in
= V
SS
or V
DD
,
Switch I/O: V
SS
v
V
I/O
v
V
DD
, and
DV
switch
v
500 mV
(3)
T
A
= 25_C only The
channel component,
(V
in
– V
out
)/R
on
, is
not included.)
Test Conditions
Min
Max
Min
25_C
Typ
(Note 2)
Max
125_C
Min
Max
Unit
SUPPLY REQUIREMENTS
(Voltages Referenced to V
EE
)
Power Supply Voltage
Range
Quiescent Current Per
Package
V
DD
I
DD
3.0
−
−
−
18
0.25
0.5
1.0
3.0
−
−
−
−
0.005
0.010
0.015
18
0.25
0.5
1.0
3.0
−
−
−
18
7.5
15
30
V
mA
Total Supply Current
(Dynamic Plus Quiescent,
Per Package
I
D(AV)
5.0
10
15
Typical
(0.07
mA/kHz)
f + I
DD
(0.20
mA/kHz)
f + I
DD
(0.36
mA/kHz)
f + I
DD
mA
CONTROL INPUTS
(Voltages Referenced to V
SS
)
Low−Level Input Voltage
V
IL
5.0
10
15
5.0
10
15
15
−
R
on
= per spec,
I
off
= per spec
R
on
= per spec,
I
off
= per spec
V
in
= 0 or V
DD
−
−
−
3.5
7.0
11
−
−
1.5
3.0
4.0
−
−
−
±0.1
−
−
−
−
3.5
7.0
11
−
−
2.25
4.50
6.75
2.75
5.50
8.25
±0.00001
5.0
1.5
3.0
4.0
−
−
−
±0.1
7.5
−
−
−
3.5
7.0
11
−
−
1.5
3.0
4.0
−
−
−
±1.0
−
V
High−Level Input Voltage
V
IH
V
Input Leakage Current
Input Capacitance
I
in
C
in
mA
pF
SWITCHES IN AND OUT
(Voltages Referenced to V
SS
)
Recommended
Peak−to−Peak Voltage Into
or Out of the Switch
Recommended Static or
Dynamic Voltage Across
the Switch (Note 3)
(Figure 1)
Output Offset Voltage
ON Resistance
V
I/O
−
Channel On or Off
0
V
DD
0
−
V
DD
0
V
DD
V
p–p
DV
switch
−
Channel On
0
600
0
−
600
0
300
mV
V
OO
R
on
−
5.0
10
15
5.0
10
15
15
V
in
= 0 V, No Load
DV
switch
v
500 mV
(3)
,
V
in
= V
IL
or V
IH
(Control), and V
in
=
0 to V
DD
(Switch)
−
−
−
−
−
−
−
−
800
400
220
70
50
45
±100
−
−
−
−
−
−
−
−
10
250
120
80
25
10
10
±0.05
−
1050
500
280
70
50
45
±100
−
−
−
−
−
−
−
−
−
1200
520
300
135
95
65
±1000
mV
W
DON
Resistance Between
Any Two Channels
in the Same Package
Off−Channel Leakage
Current (Figure 6)
DR
on
W
I
off
V
in
= V
IL
or V
IH
(Control) Channel to
Channel or Any One
Channel
Switch Off
−
nA
Capacitance, Switch I/O
Capacitance, Feedthrough
(Switch Off)
C
I/O
C
I/O
−
−
−
−
−
−
−
−
−
10
0.47
15
−
−
−
−
−
pF
pF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.
3. For voltage drops across the switch (DV
switch
) > 600 mV ( > 300 mV at high temperature), excessive V
DD
current may be drawn; i.e. the
current out of the switch may contain both V
DD
and switch input components. The reliability of the device will be unaffected unless the
Maximum Ratings are exceeded. (See first page of this data sheet.)
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MC14066B
ELECTRICAL CHARACTERISTICS
(Note 4) (C
L
= 50 pF, T
A
= 25_C unless otherwise noted.)
Characteristic
Propagation Delay Times
Input to Output (R
L
= 10 kW)
t
PLH
, t
PHL
= (0.17 ns/pF) C
L
+ 15.5 ns
t
PLH
, t
PHL
= (0.08 ns/pF) C
L
+ 6.0 ns
t
PLH
, t
PHL
= (0.06 ns/pF) C
L
+ 4.0 ns
Control to Output (R
L
= 1 kW) (Figure 2)
Output “1” to High Impedance
V
SS
= 0 Vdc
Symbol
t
PLH
, t
PHL
5.0
10
15
t
PHZ
5.0
10
15
t
PLZ
5.0
10
15
5.0
10
15
5.0
10
15
5.0
−
−
−
−
−
−
−
−
−
−
−
−
−
40
35
30
40
35
30
60
20
15
60
20
15
0.1
80
70
60
80
70
60
120
40
30
120
40
30
−
ns
−
−
−
20
10
7.0
40
20
15
ns
V
DD
Vdc
Min
Typ
(Note 5)
Max
Unit
ns
Output “0” to High Impedance
High Impedance to Output “1”
t
PZH
ns
High Impedance to Output “0”
t
PZL
ns
Second Harmonic Distortion
V
SS
= – 5 Vdc
(V
in
= 1.77 Vdc, RMS Centered @ 0.0 Vdc,
R
L
= 10 kW, f = 1.0 kHz)
Bandwidth (Switch ON) (Figure 3)
V
SS
= – 5 Vdc
(R
L
= 1 kW, 20 Log (V
out
/V
in
) = − 3 dB, C
L
= 50 pF,
V
in
= 5 V
p−p
)
Feedthrough Attenuation (Switch OFF)
V
SS
= – 5 Vdc
(V
in
= 5 V
p−p
, R
L
= 1 kW, f
in
= 1.0 MHz) (Figure 3)
Channel Separation (Figure 4)
(V
in
= 5 V
p−p
, R
L
= 1 kW, f
in
= 8.0 MHz)
(Switch A ON, Switch B OFF)
V
SS
= – 5 Vdc
−
%
−
5.0
−
65
−
MHz
−
−
5.0
5.0
−
−
– 50
– 50
−
−
dB
dB
Crosstalk, Control Input to Signal Output (Figure 5)
V
SS
= – 5 Vdc
(R
1
= 1 kW, R
L
= 10 kW, Control t
TLH
= t
THL
= 20 ns)
mV
p−p
−
5.0
−
300
−
4. The formulas given are for the typical characteristics only at 25_C.
5. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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